A tiny Open POWER ISA softcore written in VHDL 2008

openpowerppc64leprocessorvhdl

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Branch: master

alt-reset-address

asic-3

boxarty-20211011

branch-alias

cache-tlb-parameters-2

caravel-20210105

caravel-20210114

caravel-mpw5-20220322

caravel-mpw5-20220323

caravel-mpw6-20220530

caravel-mpw7-20220822

caravel-mpw7-20221125

core_debug-init

dcache-nc-fix

dcache-unused-sig

divider-init

fix-sdcard

fpu-constant

fpu-init

fpu-typo

gitignore

icache-insn-u-state

icache-pmu-events

icache-unused-sig

icbi-issue

jtag-port

jtag-port-2

less-fpga-init

litedram-update

liteeth-update

loadstore-init

loadstore-pmu-init

log2ceil-issue

master

nia-debug

orange-crab-freq

remove-potato-uart

trace-test

unused-sig

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microwatt/liteeth

History

Benjamin Herrenschmidt d564672a82 Regenerate litedram and liteeth ... Note: There are a few patches to upstream to fix an upstream breakage of litedram standalone generator, and fix some issues with liteeth in the way it's used on Wukong. All these have pending pull requests. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		2 years ago
..
gen-src	Add support for QMTech Wukong v2 board	2 years ago
generated	Regenerate litedram and liteeth	2 years ago
fusesoc-add-files.py	liteeth: Hook up LiteX LiteEth ethernet controller	3 years ago
liteeth.core	Add liteeth support to Nexys Video	2 years ago