A tiny Open POWER ISA softcore written in VHDL 2008
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Anton Blanchard 83fe8b629c litesdcard: Fix and regenerate Verilog 8 months ago
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gen-src litesdcard: Fix and regenerate Verilog 8 months ago
generated litesdcard: Fix and regenerate Verilog 8 months ago
fusesoc-add-files.py litesdcard: Use vendor not board type 2 years ago
litesdcard.core litesdcard: Use vendor not board type 2 years ago