A tiny Open POWER ISA softcore written in VHDL 2008
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#!/usr/bin/env python3
from pathlib import Path
from vunit import VUnit
ROOT = Path(__file__).parent
PRJ = VUnit.from_argv()
ROOT / "litedram" / "extras" / "*.vhdl",
ROOT / "litedram" / "generated" / "sim" / "*.vhdl"
] + [
for src_file in ROOT.glob("*.vhdl")
# Use multiply.vhd and not xilinx-mult.vhd. Use VHDL-based random.
if not any(exclude in str(src_file) for exclude in ["xilinx-mult", "foreign_random", "nonrandom"])
PRJ.add_library("unisim").add_source_files(ROOT / "sim-unisim" / "*.vhdl")
PRJ.set_sim_option("disable_ieee_warnings", True)