A tiny Open POWER ISA softcore written in VHDL 2008

openpowerppc64leprocessorvhdl

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Branch: master

alt-reset-address

asic-3

boxarty-20211011

branch-alias

cache-tlb-parameters-2

caravel-20210105

caravel-20210114

caravel-mpw5-20220322

caravel-mpw5-20220323

caravel-mpw6-20220530

caravel-mpw7-20220822

caravel-mpw7-20221125

core_debug-init

dcache-nc-fix

dcache-unused-sig

divider-init

fix-sdcard

fpu-constant

fpu-init

fpu-typo

gitignore

icache-insn-u-state

icache-pmu-events

icache-unused-sig

icbi-issue

jtag-port

jtag-port-2

less-fpga-init

litedram-update

liteeth-update

loadstore-init

loadstore-pmu-init

log2ceil-issue

master

nia-debug

orange-crab-freq

remove-potato-uart

trace-test

unused-sig

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microwatt/sim-unisim

History

Benjamin Herrenschmidt ee52fd4d80 Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs ... This adds a simple bus that can be mastered from an external system via JTAG, which will be used to hookup various debug modules. It's loosely based on the RiscV model (hence the DMI name). The module currently only supports hooking up to a Xilinx BSCANE2 but it shouldn't be too hard to adapt it to support different TAPs if necessary. The JTAG protocol proper is not exactly the RiscV one at this point, though I might still change it. This comes with some sim variants of Xilinx BSCANE2 and BUFG and a test bench. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		4 years ago
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BSCANE2.vhdl	Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs	4 years ago
BUFG.vhdl	Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs	4 years ago
unisim_vcomponents.vhdl	Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs	4 years ago