A tiny Open POWER ISA softcore written in VHDL 2008

openpowerppc64leprocessorvhdl

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Branch: master

alt-reset-address

asic-3

boxarty-20211011

branch-alias

cache-tlb-parameters-2

caravel-20210105

caravel-20210114

caravel-mpw5-20220322

caravel-mpw5-20220323

caravel-mpw6-20220530

caravel-mpw7-20220822

caravel-mpw7-20221125

core_debug-init

dcache-nc-fix

dcache-unused-sig

divider-init

fix-sdcard

fpu-constant

fpu-init

fpu-typo

gitignore

icache-insn-u-state

icache-pmu-events

icache-unused-sig

icbi-issue

jtag-port

jtag-port-2

less-fpga-init

litedram-update

liteeth-update

loadstore-init

loadstore-pmu-init

log2ceil-issue

master

nia-debug

orange-crab-freq

remove-potato-uart

trace-test

unused-sig

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microwatt/verilator

History

Anton Blanchard 8acd5a5607 verilator: Specify top level module ... While verilator finds the correct top level module with the current setup, if we start adding simulation models it can get confused. Explicitly specify the top level module. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>		2 years ago
..
microwatt-verilator.cpp	verilator: Specify top level module	2 years ago
uart-verilator.c	Pass clock frequency to UART sim wrapper	3 years ago