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469 lines
10 KiB
C
469 lines
10 KiB
C
#include <stddef.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include "console.h"
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extern int test_read(long *addr, long *ret, long init);
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extern int test_write(long *addr, long val);
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static inline void do_tlbie(unsigned long rb, unsigned long rs)
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{
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__asm__ volatile("tlbie %0,%1" : : "r" (rb), "r" (rs) : "memory");
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}
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static inline unsigned long mfspr(int sprnum)
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{
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long val;
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__asm__ volatile("mfspr %0,%1" : "=r" (val) : "i" (sprnum));
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return val;
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}
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static inline void mtspr(int sprnum, unsigned long val)
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{
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__asm__ volatile("mtspr %0,%1" : : "i" (sprnum), "r" (val));
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}
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static inline void store_pte(unsigned long *p, unsigned long pte)
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{
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__asm__ volatile("stdbrx %1,0,%0" : : "r" (p), "r" (pte) : "memory");
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}
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void print_string(const char *str)
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{
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for (; *str; ++str)
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putchar(*str);
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}
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void print_hex(unsigned long val)
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{
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int i, x;
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for (i = 60; i >= 0; i -= 4) {
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x = (val >> i) & 0xf;
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if (x >= 10)
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putchar(x + 'a' - 10);
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else
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putchar(x + '0');
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}
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}
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// i < 100
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void print_test_number(int i)
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{
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print_string("test ");
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putchar(48 + i/10);
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putchar(48 + i%10);
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putchar(':');
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}
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#define CACHE_LINE_SIZE 64
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void zero_memory(void *ptr, unsigned long nbytes)
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{
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unsigned long nb, i, nl;
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void *p;
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for (; nbytes != 0; nbytes -= nb, ptr += nb) {
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nb = -((unsigned long)ptr) & (CACHE_LINE_SIZE - 1);
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if (nb == 0 && nbytes >= CACHE_LINE_SIZE) {
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nl = nbytes / CACHE_LINE_SIZE;
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p = ptr;
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for (i = 0; i < nl; ++i) {
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__asm__ volatile("dcbz 0,%0" : : "r" (p) : "memory");
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p += CACHE_LINE_SIZE;
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}
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nb = nl * CACHE_LINE_SIZE;
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} else {
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if (nb > nbytes)
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nb = nbytes;
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for (i = 0; i < nb; ++i)
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((unsigned char *)ptr)[i] = 0;
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}
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}
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}
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#define PERM_EX 0x001
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#define PERM_WR 0x002
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#define PERM_RD 0x004
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#define PERM_PRIV 0x008
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#define ATTR_NC 0x020
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#define CHG 0x080
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#define REF 0x100
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#define DFLT_PERM (PERM_WR | PERM_RD | REF | CHG)
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/*
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* Set up an MMU translation tree using memory starting at the 64k point.
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* We use 2 levels, mapping 2GB (the minimum size possible), with a
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* 8kB PGD level pointing to 4kB PTE pages.
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*/
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unsigned long *pgdir = (unsigned long *) 0x10000;
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unsigned long free_ptr = 0x12000;
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void *eas_mapped[4];
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int neas_mapped;
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void init_mmu(void)
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{
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zero_memory(pgdir, 1024 * sizeof(unsigned long));
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/* RTS = 0 (2GB address space), RPDS = 10 (1024-entry top level) */
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mtspr(720, (unsigned long) pgdir | 10);
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do_tlbie(0xc00, 0); /* invalidate all TLB entries */
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}
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static unsigned long *read_pgd(unsigned long i)
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{
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unsigned long ret;
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__asm__ volatile("ldbrx %0,%1,%2" : "=r" (ret) : "b" (pgdir),
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"r" (i * sizeof(unsigned long)));
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return (unsigned long *) (ret & 0x00ffffffffffff00);
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}
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void map(void *ea, void *pa, unsigned long perm_attr)
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{
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unsigned long epn = (unsigned long) ea >> 12;
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unsigned long i, j;
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unsigned long *ptep;
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i = (epn >> 9) & 0x3ff;
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j = epn & 0x1ff;
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if (pgdir[i] == 0) {
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zero_memory((void *)free_ptr, 512 * sizeof(unsigned long));
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store_pte(&pgdir[i], 0x8000000000000000 | free_ptr | 9);
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free_ptr += 512 * sizeof(unsigned long);
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}
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ptep = read_pgd(i);
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store_pte(&ptep[j], 0xc000000000000000 | ((unsigned long)pa & 0x00fffffffffff000) | perm_attr);
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eas_mapped[neas_mapped++] = ea;
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}
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void unmap(void *ea)
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{
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unsigned long epn = (unsigned long) ea >> 12;
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unsigned long i, j;
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unsigned long *ptep;
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i = (epn >> 9) & 0x3ff;
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j = epn & 0x1ff;
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if (pgdir[i] == 0)
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return;
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ptep = read_pgd(i);
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ptep[j] = 0;
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do_tlbie(((unsigned long)ea & ~0xfff), 0);
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}
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void unmap_all(void)
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{
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int i;
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for (i = 0; i < neas_mapped; ++i)
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unmap(eas_mapped[i]);
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neas_mapped = 0;
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}
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int mmu_test_1(void)
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{
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long *ptr = (long *) 0x123000;
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long val;
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/* this should fail */
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if (test_read(ptr, &val, 0xdeadbeefd00d))
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return 1;
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/* dest reg of load should be unchanged */
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if (val != 0xdeadbeefd00d)
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return 2;
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/* DAR and DSISR should be set correctly */
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if (mfspr(19) != (long) ptr || mfspr(18) != 0x40000000)
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return 3;
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return 0;
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}
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int mmu_test_2(void)
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{
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long *mem = (long *) 0x4000;
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long *ptr = (long *) 0x124000;
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long *ptr2 = (long *) 0x1124000;
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long val;
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/* create PTE */
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map(ptr, mem, DFLT_PERM);
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/* initialize the memory content */
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mem[33] = 0xbadc0ffee;
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/* this should succeed and be a cache miss */
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if (!test_read(&ptr[33], &val, 0xdeadbeefd00d))
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return 1;
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/* dest reg of load should have the value written */
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if (val != 0xbadc0ffee)
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return 2;
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/* load a second TLB entry in the same set as the first */
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map(ptr2, mem, DFLT_PERM);
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/* this should succeed and be a cache hit */
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if (!test_read(&ptr2[33], &val, 0xdeadbeefd00d))
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return 3;
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/* dest reg of load should have the value written */
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if (val != 0xbadc0ffee)
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return 4;
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/* check that the first entry still works */
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if (!test_read(&ptr[33], &val, 0xdeadbeefd00d))
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return 5;
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if (val != 0xbadc0ffee)
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return 6;
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return 0;
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}
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int mmu_test_3(void)
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{
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long *mem = (long *) 0x5000;
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long *ptr = (long *) 0x149000;
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long val;
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/* create PTE */
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map(ptr, mem, DFLT_PERM);
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/* initialize the memory content */
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mem[45] = 0xfee1800d4ea;
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/* this should succeed and be a cache miss */
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if (!test_read(&ptr[45], &val, 0xdeadbeefd0d0))
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return 1;
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/* dest reg of load should have the value written */
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if (val != 0xfee1800d4ea)
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return 2;
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/* remove the PTE */
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unmap(ptr);
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/* this should fail */
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if (test_read(&ptr[45], &val, 0xdeadbeefd0d0))
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return 3;
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/* dest reg of load should be unchanged */
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if (val != 0xdeadbeefd0d0)
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return 4;
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/* DAR and DSISR should be set correctly */
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if (mfspr(19) != (long) &ptr[45] || mfspr(18) != 0x40000000)
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return 5;
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return 0;
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}
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int mmu_test_4(void)
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{
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long *mem = (long *) 0x6000;
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long *ptr = (long *) 0x10a000;
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long *ptr2 = (long *) 0x110a000;
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long val;
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/* create PTE */
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map(ptr, mem, DFLT_PERM);
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/* initialize the memory content */
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mem[27] = 0xf00f00f00f00;
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/* this should succeed and be a cache miss */
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if (!test_write(&ptr[27], 0xe44badc0ffee))
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return 1;
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/* memory should now have the value written */
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if (mem[27] != 0xe44badc0ffee)
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return 2;
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/* load a second TLB entry in the same set as the first */
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map(ptr2, mem, DFLT_PERM);
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/* this should succeed and be a cache hit */
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if (!test_write(&ptr2[27], 0x6e11ae))
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return 3;
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/* memory should have the value written */
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if (mem[27] != 0x6e11ae)
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return 4;
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/* check that the first entry still exists */
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/* (assumes TLB is 2-way associative or more) */
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if (!test_read(&ptr[27], &val, 0xdeadbeefd00d))
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return 5;
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if (val != 0x6e11ae)
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return 6;
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return 0;
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}
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int mmu_test_5(void)
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{
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long *mem = (long *) 0x7ffd;
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long *ptr = (long *) 0x39fffd;
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long val;
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/* create PTE */
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map(ptr, mem, DFLT_PERM);
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/* this should fail */
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if (test_read(ptr, &val, 0xdeadbeef0dd0))
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return 1;
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/* dest reg of load should be unchanged */
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if (val != 0xdeadbeef0dd0)
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return 2;
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/* DAR and DSISR should be set correctly */
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if (mfspr(19) != ((long)ptr & ~0xfff) + 0x1000 || mfspr(18) != 0x40000000)
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return 3;
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return 0;
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}
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int mmu_test_6(void)
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{
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long *mem = (long *) 0x7ffd;
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long *ptr = (long *) 0x39fffd;
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/* create PTE */
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map(ptr, mem, DFLT_PERM);
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/* initialize memory */
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*mem = 0x123456789abcdef0;
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/* this should fail */
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if (test_write(ptr, 0xdeadbeef0dd0))
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return 1;
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/* DAR and DSISR should be set correctly */
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if (mfspr(19) != ((long)ptr & ~0xfff) + 0x1000 || mfspr(18) != 0x42000000)
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return 2;
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return 0;
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}
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int mmu_test_7(void)
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{
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long *mem = (long *) 0x4000;
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long *ptr = (long *) 0x124000;
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long val;
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*mem = 0x123456789abcdef0;
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/* create PTE without R or C */
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map(ptr, mem, PERM_RD | PERM_WR);
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/* this should fail */
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if (test_read(ptr, &val, 0xdeadd00dbeef))
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return 1;
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/* dest reg of load should be unchanged */
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if (val != 0xdeadd00dbeef)
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return 2;
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/* DAR and DSISR should be set correctly */
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if (mfspr(19) != (long) ptr || mfspr(18) != 0x00040000)
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return 3;
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/* this should fail */
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if (test_write(ptr, 0xdeadbeef0dd0))
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return 4;
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/* DAR and DSISR should be set correctly */
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if (mfspr(19) != (long)ptr || mfspr(18) != 0x02040000)
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return 5;
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/* memory should be unchanged */
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if (*mem != 0x123456789abcdef0)
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return 6;
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return 0;
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}
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int mmu_test_8(void)
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{
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long *mem = (long *) 0x4000;
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long *ptr = (long *) 0x124000;
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long val;
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*mem = 0x123456789abcdef0;
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/* create PTE with R but not C */
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map(ptr, mem, REF | PERM_RD | PERM_WR);
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/* this should succeed */
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if (!test_read(ptr, &val, 0xdeadd00dbeef))
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return 1;
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/* this should fail */
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if (test_write(ptr, 0xdeadbeef0dd1))
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return 2;
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/* DAR and DSISR should be set correctly */
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if (mfspr(19) != (long)ptr || mfspr(18) != 0x02040000)
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return 3;
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/* memory should be unchanged */
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if (*mem != 0x123456789abcdef0)
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return 4;
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return 0;
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}
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int mmu_test_9(void)
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{
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long *mem = (long *) 0x4000;
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long *ptr = (long *) 0x124000;
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long val;
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*mem = 0x123456789abcdef0;
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/* create PTE without read or write permission */
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map(ptr, mem, REF);
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/* this should fail */
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if (test_read(ptr, &val, 0xdeadd00dbeef))
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return 1;
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/* dest reg of load should be unchanged */
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if (val != 0xdeadd00dbeef)
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return 2;
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/* DAR and DSISR should be set correctly */
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if (mfspr(19) != (long) ptr || mfspr(18) != 0x08000000)
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return 3;
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/* this should fail */
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if (test_write(ptr, 0xdeadbeef0dd1))
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return 4;
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/* DAR and DSISR should be set correctly */
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if (mfspr(19) != (long)ptr || mfspr(18) != 0x0a000000)
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return 5;
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/* memory should be unchanged */
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if (*mem != 0x123456789abcdef0)
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return 6;
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return 0;
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}
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int mmu_test_10(void)
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{
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long *mem = (long *) 0x4000;
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long *ptr = (long *) 0x124000;
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long val;
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*mem = 0x123456789abcdef0;
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/* create PTE with read but not write permission */
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map(ptr, mem, REF | PERM_RD);
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/* this should succeed */
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if (!test_read(ptr, &val, 0xdeadd00dbeef))
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return 1;
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/* this should fail */
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if (test_write(ptr, 0xdeadbeef0dd1))
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return 2;
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/* DAR and DSISR should be set correctly */
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if (mfspr(19) != (long)ptr || mfspr(18) != 0x0a000000)
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return 3;
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/* memory should be unchanged */
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if (*mem != 0x123456789abcdef0)
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return 4;
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return 0;
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}
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int fail = 0;
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void do_test(int num, int (*test)(void))
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{
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int ret;
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mtspr(18, 0);
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mtspr(19, 0);
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unmap_all();
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print_test_number(num);
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ret = test();
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if (ret == 0) {
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print_string("PASS\r\n");
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} else {
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fail = 1;
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print_string("FAIL ");
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putchar(ret + '0');
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print_string(" DAR=");
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print_hex(mfspr(19));
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print_string(" DSISR=");
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print_hex(mfspr(18));
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print_string("\r\n");
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}
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}
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int main(void)
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{
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potato_uart_init();
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init_mmu();
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do_test(1, mmu_test_1);
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do_test(2, mmu_test_2);
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do_test(3, mmu_test_3);
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do_test(4, mmu_test_4);
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do_test(5, mmu_test_5);
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do_test(6, mmu_test_6);
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do_test(7, mmu_test_7);
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do_test(8, mmu_test_8);
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do_test(9, mmu_test_9);
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do_test(10, mmu_test_10);
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return fail;
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}
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