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caravel-mpw7-20221125
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litedram-update
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microwatt/litedram/gen-src/sdram_init
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Benjamin Herrenschmidt 025cf5efe8 syscon: Add syscon registers 
These provides some info about the SoC (though it's still somewhat
incomplete and needs more work, see comments).

There's also a control register for selecting DRAM vs. BRAM at 0
(and for soft-resetting the SoC but that isn't wired up yet).

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 		4 years ago
..
include litedram: Add basic support for LiteX LiteDRAM 4 years ago
libc litedram: Add basic support for LiteX LiteDRAM 4 years ago
Makefile litedram: Add basic support for LiteX LiteDRAM 4 years ago
bin2hex.py litedram: Add basic support for LiteX LiteDRAM 4 years ago
head.S litedram: Add basic support for LiteX LiteDRAM 4 years ago
main.c syscon: Add syscon registers 4 years ago
sdram_init.lds litedram: Add basic support for LiteX LiteDRAM 4 years ago