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Anton Blanchard 03fd06deaf Rework SOC reset ... The old reset code was overly complicated and never worked properly. Replace it with a simpler sequence that uses a couple of shift registers to assert resets: - Wait a number of external clock cycles before removing reset from the PLL. - After the PLL locks and the external reset button isn't pressed, wait a number of PLL clock cycles before removing reset from the SOC. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>		5 years ago
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LICENSE	Initial import of microwatt	5 years ago
arty_a7-35.xdc	Rename a few reset signals	5 years ago
clk_gen_bypass.vhd	Rework SOC reset	5 years ago
clk_gen_plle2.vhd	Rework SOC reset	5 years ago
firmware.hex	Add a few more FPGA related files	5 years ago
hello_world.hex	Rebuild hello world assuming a 50MHz clock	5 years ago
nexys-video.xdc	Rename a few reset signals	5 years ago
nexys_a7.xdc	Rename a few reset signals	5 years ago
nodivide.patch	Add a few more FPGA related files	5 years ago
pp_fifo.vhd	Initial import of microwatt	5 years ago
pp_soc_memory.vhd	Fix ghdl build error with pp_soc_memory	5 years ago
pp_soc_uart.vhd	Initial import of microwatt	5 years ago
pp_utilities.vhd	Initial import of microwatt	5 years ago
soc_reset.vhdl	Rework SOC reset	5 years ago
soc_reset_tb.vhdl	Rework SOC reset	5 years ago
toplevel.vhd	Rework SOC reset	5 years ago