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1441b2a859
This implements in the L2 cache the feature already in the L1s allowing a request to be completed before the end of a refill using partial line valid bits, and starting a refill from the row of the first miss on that line instead of the beginning of the line. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
4 years ago | |
|---|---|---|
| .. | ||
| fusesoc-add-files.py | 5 years ago | |
| litedram-wrapper-l2.vhdl | 4 years ago | |
| sim_dram_verilate.mk | 5 years ago | |
| sim_litedram.vhdl | 5 years ago | |
| sim_litedram_c.cpp | 5 years ago | |
| wave.gtkw | 5 years ago | |
| wave.opt | 5 years ago | |
| wave_tb.gtkw | 4 years ago | |