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Benjamin Herrenschmidt 1441b2a859 litedram: l2: Latency improvements ... This implements in the L2 cache the feature already in the L1s allowing a request to be completed before the end of a refill using partial line valid bits, and starting a refill from the row of the first miss on that line instead of the beginning of the line. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		4 years ago
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fusesoc-add-files.py	litedram: Remove old "VexRiscV" based initializations	4 years ago
litedram-wrapper-l2.vhdl	litedram: l2: Latency improvements	4 years ago
sim_dram_verilate.mk	litedram: Add simulation support	4 years ago
sim_litedram.vhdl	litedram: Add simulation support	4 years ago
sim_litedram_c.cpp	litedram: Add simulation support	4 years ago
wave.gtkw	litedram: Add an L2 cache with store queue	4 years ago
wave.opt	litedram: Add an L2 cache with store queue	4 years ago
wave_tb.gtkw	litedram: l2: Latency improvements	4 years ago