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87 lines
2.8 KiB
VHDL
87 lines
2.8 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity cordic_wb is
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port(
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clk : in std_ulogic;
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rst : in std_ulogic;
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-- Wishbone IO interface (Microwatt)
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wb_adr_i : in std_ulogic_vector(29 downto 0);
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wb_dat_i : in std_ulogic_vector(31 downto 0);
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wb_dat_o : out std_ulogic_vector(31 downto 0);
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wb_we_i : in std_ulogic;
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wb_stb_i : in std_ulogic;
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wb_cyc_i : in std_ulogic;
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wb_ack_o : out std_ulogic;
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-- CORDIC core interface
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cordic_x : out std_ulogic_vector(31 downto 0);
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cordic_y : out std_ulogic_vector(31 downto 0);
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cordic_start : out std_ulogic;
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cordic_done : in std_ulogic;
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cordic_result : in std_ulogic_vector(31 downto 0)
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);
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end entity cordic_wb;
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architecture rtl of cordic_wb is
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signal x_reg : std_ulogic_vector(31 downto 0) := (others => '0');
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signal y_reg : std_ulogic_vector(31 downto 0) := (others => '0');
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signal start_reg : std_ulogic := '0';
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begin
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-- Drive CORDIC core
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cordic_x <= x_reg;
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cordic_y <= y_reg;
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cordic_start <= start_reg;
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-- Wishbone slave
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process(clk)
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variable addr : std_ulogic_vector(2 downto 0);
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begin
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if rising_edge(clk) then
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wb_ack_o <= '0';
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if rst = '1' then
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x_reg <= (others => '0');
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y_reg <= (others => '0');
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start_reg <= '0';
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wb_dat_o <= (others => '0');
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elsif wb_cyc_i = '1' and wb_stb_i = '1' then
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wb_ack_o <= '1';
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addr := wb_adr_i(4 downto 2); -- word offsets
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if wb_we_i = '1' then
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-- WRITE
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case addr is
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when "000" => x_reg <= wb_dat_i; -- 0x00
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when "001" => y_reg <= wb_dat_i; -- 0x04
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when "010" => start_reg <= wb_dat_i(0); -- 0x08
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when others => null;
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end case;
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else
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-- READ
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case addr is
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when "000" => wb_dat_o <= x_reg; -- 0x00
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when "001" => wb_dat_o <= y_reg; -- 0x04
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when "011" => wb_dat_o <= (31 downto 1 => '0') & cordic_done; -- 0x0C
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when "100" => wb_dat_o <= cordic_result; -- 0x10
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when others => wb_dat_o <= (others => '0');
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end case;
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end if;
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end if;
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-- Auto-clear start when done
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if cordic_done = '1' then
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start_reg <= '0';
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end if;
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end if;
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end process;
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end architecture rtl;
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