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58 lines
1.3 KiB
VHDL
58 lines
1.3 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.common.all;
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use work.wishbone_types.all;
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entity core_tb is
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end core_tb;
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architecture behave of core_tb is
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signal clk, rst: std_logic;
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signal wishbone_in : wishbone_slave_out;
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signal wishbone_out : wishbone_master_out;
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signal registers : regfile;
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signal terminate : std_ulogic;
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-- testbench signals
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constant clk_period : time := 10 ns;
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begin
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core_0: entity work.core
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generic map (SIM => true)
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port map (clk => clk, rst => rst, wishbone_in => wishbone_in,
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wishbone_out => wishbone_out, registers => registers, terminate_out => terminate);
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simple_ram_0: entity work.simple_ram_behavioural
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generic map ( filename => "simple_ram_behavioural.bin", size => 524288)
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port map (clk => clk, rst => rst, wishbone_in => wishbone_out, wishbone_out => wishbone_in);
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clk_process: process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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rst_process: process
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begin
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rst <= '1';
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wait for 10*clk_period;
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rst <= '0';
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wait;
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end process;
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dump_registers: process(all)
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begin
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if terminate = '1' then
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loop_0: for i in 0 to 31 loop
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report "REG " & to_hstring(registers(i));
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end loop loop_0;
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assert false report "end of test" severity failure;
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end if;
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end process;
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end;
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