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70 lines
2.1 KiB
VHDL
70 lines
2.1 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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entity register_file is
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port(
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clk : in std_logic;
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d_in : in Decode2ToRegisterFileType;
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d_out : out RegisterFileToDecode2Type;
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w_in : in WritebackToRegisterFileType;
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-- debug
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registers_out : out regfile
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);
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end entity register_file;
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architecture behaviour of register_file is
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signal registers : regfile := (others => (others => '0'));
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begin
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-- synchronous writes
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register_write_0: process(clk)
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begin
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if rising_edge(clk) then
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if w_in.write_enable = '1' then
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assert not(is_x(w_in.write_data)) and not(is_x(w_in.write_reg)) severity failure;
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report "Writing GPR " & to_hstring(w_in.write_reg) & " " & to_hstring(w_in.write_data);
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registers(to_integer(unsigned(w_in.write_reg))) <= w_in.write_data;
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end if;
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end if;
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end process register_write_0;
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-- asynchronous reads
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register_read_0: process(all)
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begin
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if d_in.read1_enable = '1' then
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report "Reading GPR " & to_hstring(d_in.read1_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read1_reg))));
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end if;
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if d_in.read2_enable = '1' then
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report "Reading GPR " & to_hstring(d_in.read2_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read2_reg))));
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end if;
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if d_in.read3_enable = '1' then
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report "Reading GPR " & to_hstring(d_in.read3_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read3_reg))));
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end if;
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d_out.read1_data <= registers(to_integer(unsigned(d_in.read1_reg)));
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d_out.read2_data <= registers(to_integer(unsigned(d_in.read2_reg)));
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d_out.read3_data <= registers(to_integer(unsigned(d_in.read3_reg)));
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-- Forward any written data
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--if w_in.write_enable = '1' then
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--if d_in.read1_reg = w_in.write_reg then
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--d_out.read1_data <= w_in.write_data;
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--end if;
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--if d_in.read2_reg = w_in.write_reg then
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--d_out.read2_data <= w_in.write_data;
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--end if;
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--if d_in.read3_reg = w_in.write_reg then
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--d_out.read3_data <= w_in.write_data;
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--end if;
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--end if;
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end process register_read_0;
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-- debug
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registers_out <= registers;
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end architecture behaviour;
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