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66 lines
1.6 KiB
VHDL
66 lines
1.6 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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entity cr_file is
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port(
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clk : in std_logic;
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d_in : in Decode2ToCrFileType;
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d_out : out CrFileToDecode2Type;
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w_in : in WritebackToCrFileType
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);
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end entity cr_file;
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architecture behaviour of cr_file is
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signal crs : std_ulogic_vector(31 downto 0) := (others => '0');
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begin
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-- synchronous writes
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cr_write_0: process(clk)
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variable hi, lo : integer := 0;
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begin
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if rising_edge(clk) then
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if w_in.write_cr_enable = '1' then
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report "Writing " & to_hstring(w_in.write_cr_data) & " to CR mask " & to_hstring(w_in.write_cr_mask);
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for i in 0 to 7 loop
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if w_in.write_cr_mask(i) = '1' then
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lo := i*4;
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hi := lo + 3;
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crs(hi downto lo) <= w_in.write_cr_data(hi downto lo);
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end if;
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end loop;
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end if;
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end if;
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end process cr_write_0;
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-- asynchronous reads
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cr_read_0: process(all)
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variable hi, lo : integer := 0;
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begin
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--lo := (7-d_in.read_cr_nr_1)*4;
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--hi := lo + 3;
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--report "read " & integer'image(d_in.read_cr_nr_1) & " from CR " & to_hstring(crs(hi downto lo));
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--d_out.read_cr_data_1 <= crs(hi downto lo);
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-- Also return the entire CR to make mfcrf easier for now
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report "read CR " & to_hstring(crs);
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d_out.read_cr_data <= crs;
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-- -- Forward any written data
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-- if w_in.write_cr_enable = '1' then
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-- if d_in.read_cr_nr_1 = w_in.write_cr_nr then
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-- d_out.read_cr_data_1 <= w_in.write_cr_data;
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-- end if;
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-- if d_in.read_cr_nr_2 = w_in.write_cr_nr then
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-- d_out.read_cr_data_2 <= w_in.write_cr_data;
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-- end if;
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-- end if;
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end process cr_read_0;
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end architecture behaviour;
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