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96 lines
2.9 KiB
VHDL
96 lines
2.9 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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entity zero_counter is
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port (
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clk : in std_logic;
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rs : in std_ulogic_vector(63 downto 0);
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count_right : in std_ulogic;
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is_32bit : in std_ulogic;
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result : out std_ulogic_vector(63 downto 0)
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);
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end entity zero_counter;
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architecture behaviour of zero_counter is
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-- Reverse the order of bits in a word
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function bit_reverse(a: std_ulogic_vector) return std_ulogic_vector is
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variable ret: std_ulogic_vector(a'left downto a'right);
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begin
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for i in a'right to a'left loop
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ret(a'left + a'right - i) := a(i);
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end loop;
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return ret;
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end;
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-- If there is only one bit set in a doubleword, return its bit number
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-- (counting from the right). Each bit of the result is obtained by
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-- ORing together 32 bits of the input:
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-- bit 0 = a[1] or a[3] or a[5] or ...
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-- bit 1 = a[2] or a[3] or a[6] or a[7] or ...
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-- bit 2 = a[4..7] or a[12..15] or ...
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-- bit 5 = a[32..63] ORed together
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function bit_number(a: std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
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variable ret: std_ulogic_vector(5 downto 0);
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variable stride: natural;
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variable bit: std_ulogic;
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variable k: natural;
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begin
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stride := 2;
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for i in 0 to 5 loop
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bit := '0';
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for j in 0 to (64 / stride) - 1 loop
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k := j * stride;
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bit := bit or (or a(k + stride - 1 downto k + (stride / 2)));
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end loop;
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ret(i) := bit;
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stride := stride * 2;
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end loop;
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return ret;
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end;
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signal inp : std_ulogic_vector(63 downto 0);
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signal sum : std_ulogic_vector(64 downto 0);
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signal msb_r : std_ulogic;
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signal onehot : std_ulogic_vector(63 downto 0);
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signal onehot_r : std_ulogic_vector(63 downto 0);
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signal bitnum : std_ulogic_vector(5 downto 0);
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begin
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countzero_r: process(clk)
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begin
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if rising_edge(clk) then
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msb_r <= sum(64);
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onehot_r <= onehot;
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end if;
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end process;
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countzero: process(all)
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begin
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if is_32bit = '0' then
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if count_right = '0' then
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inp <= bit_reverse(rs);
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else
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inp <= rs;
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end if;
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else
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inp(63 downto 32) <= x"FFFFFFFF";
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if count_right = '0' then
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inp(31 downto 0) <= bit_reverse(rs(31 downto 0));
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else
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inp(31 downto 0) <= rs(31 downto 0);
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end if;
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end if;
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sum <= std_ulogic_vector(unsigned('0' & not inp) + 1);
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onehot <= sum(63 downto 0) and inp;
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-- The following occurs after a clock edge
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bitnum <= bit_number(onehot_r);
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result <= x"00000000000000" & "0" & msb_r & bitnum;
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end process;
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end behaviour;
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