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40 lines
851 B
VHDL
40 lines
851 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.ALL;
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library unisim;
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use unisim.vcomponents.all;
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entity BSCANE2 is
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generic(jtag_chain: INTEGER);
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port(capture : out std_logic;
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drck : out std_logic;
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reset : out std_logic;
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runtest : out std_logic;
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sel : out std_logic;
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shift : out std_logic;
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tck : out std_logic;
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tdi : out std_logic;
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tms : out std_logic;
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update : out std_logic;
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tdo : in std_logic
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);
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end BSCANE2;
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architecture behaviour of BSCANE2 is
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alias j : glob_jtag_t is glob_jtag;
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begin
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sel <= j.sel(jtag_chain);
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tck <= j.tck;
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drck <= tck and sel and (capture or shift);
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capture <= j.capture;
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reset <= j.reset;
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runtest <= j.runtest;
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shift <= j.shift;
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tdi <= j.tdi;
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tms <= j.tms;
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update <= j.update;
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j.tdo <= tdo;
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end architecture behaviour;
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