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microwatt/sim-unisim/BUFG.vhdl

13 lines
201 B
VHDL

library IEEE;
use IEEE.std_logic_1164.all;
entity BUFG is
port(I : in std_logic;
O : out std_logic
);
end BUFG;
architecture behaviour of BUFG is
begin
O <= I;
end architecture behaviour;