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2e3668f840
We need to expose all the input, output and output enable SPI lines in order to use QSPI. Remove the reset controller and PLL, since we are driving these directly from caravel. |
4 years ago | |
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| .. | ||
| LICENSE | ||
| acorn-cle-215.xdc | ||
| arty_a7.xdc | ||
| clk_gen_bypass.vhd | ||
| clk_gen_ecp5.vhd | ||
| clk_gen_mcmm.vhd | ||
| clk_gen_plle2.vhd | ||
| cmod_a7-35.xdc | ||
| firmware.hex | ||
| fpga-random.vhdl | ||
| fpga-random.xdc | ||
| genesys2.xdc | 5 years ago | |
| hello_world.hex | ||
| main_bram.vhdl | ||
| main_bram_caravel.vhdl | 4 years ago | |
| nexys-video.xdc | ||
| nexys_a7.xdc | ||
| pp_fifo.vhd | ||
| pp_soc_uart.vhd | ||
| pp_utilities.vhd | ||
| soc_reset.vhdl | ||
| soc_reset_tb.vhdl | ||
| top-acorn-cle-215.vhdl | ||
| top-arty.vhdl | 5 years ago | |
| top-caravel.vhdl | 4 years ago | |
| top-generic.vhdl | 4 years ago | |
| top-genesys2.vhdl | 5 years ago | |
| top-nexys-video.vhdl | 5 years ago | |