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195 lines
7.2 KiB
VHDL
195 lines
7.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.decode_types.all;
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use work.ppc_fx_insns.all;
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entity logical is
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port (
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rs : in std_ulogic_vector(63 downto 0);
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rb : in std_ulogic_vector(63 downto 0);
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op : in insn_type_t;
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invert_in : in std_ulogic;
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invert_out : in std_ulogic;
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is_signed : in std_ulogic;
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result : out std_ulogic_vector(63 downto 0);
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datalen : in std_logic_vector(3 downto 0)
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);
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end entity logical;
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architecture behaviour of logical is
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signal par0, par1 : std_ulogic;
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signal parity : std_ulogic_vector(63 downto 0);
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signal permute : std_ulogic_vector(7 downto 0);
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function bcd_to_dpd(bcd: std_ulogic_vector(11 downto 0)) return std_ulogic_vector is
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variable dpd: std_ulogic_vector(9 downto 0);
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variable a, b, c, d, e, f, g, h, i, j, k, m: std_ulogic;
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begin
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-- The following equations are copied from PowerISA v3.0B Book 1 appendix B
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a := bcd(11);
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b := bcd(10);
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c := bcd(9);
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d := bcd(8);
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e := bcd(7);
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f := bcd(6);
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g := bcd(5);
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h := bcd(4);
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i := bcd(3);
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j := bcd(2);
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k := bcd(1);
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m := bcd(0);
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dpd(9) := (f and a and i and not e) or (j and a and not i) or (b and not a);
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dpd(8) := (g and a and i and not e) or (k and a and not i) or (c and not a);
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dpd(7) := d;
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dpd(6) := (j and not a and e and not i) or (f and not i and not e) or
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(f and not a and not e) or (e and i);
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dpd(5) := (k and not a and e and not i) or (g and not i and not e) or
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(g and not a and not e) or (a and i);
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dpd(4) := h;
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dpd(3) := a or e or i;
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dpd(2) := (not e and j and not i) or (e and i) or a;
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dpd(1) := (not a and k and not i) or (a and i) or e;
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dpd(0) := m;
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return dpd;
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end;
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function dpd_to_bcd(dpd: std_ulogic_vector(9 downto 0)) return std_ulogic_vector is
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variable bcd: std_ulogic_vector(11 downto 0);
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variable p, q, r, s, t, u, v, w, x, y: std_ulogic;
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begin
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-- The following equations are copied from PowerISA v3.0B Book 1 appendix B
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p := dpd(9);
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q := dpd(8);
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r := dpd(7);
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s := dpd(6);
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t := dpd(5);
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u := dpd(4);
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v := dpd(3);
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w := dpd(2);
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x := dpd(1);
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y := dpd(0);
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bcd(11) := (not s and v and w) or (t and v and w and s) or (v and w and not x);
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bcd(10) := (p and s and x and not t) or (p and not w) or (p and not v);
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bcd(9) := (q and s and x and not t) or (q and not w) or (q and not v);
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bcd(8) := r;
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bcd(7) := (v and not w and x) or (s and v and w and x) or (not t and v and w and x);
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bcd(6) := (p and t and v and w and x and not s) or (s and not x and v) or
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(s and not v);
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bcd(5) := (q and t and w and v and x and not s) or (t and not x and v) or
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(t and not v);
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bcd(4) := u;
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bcd(3) := (t and v and w and x) or (s and v and w and x) or (v and not w and not x);
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bcd(2) := (p and not s and not t and w and v) or (s and v and not w and x) or
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(p and w and not x and v) or (w and not v);
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bcd(1) := (q and not s and not t and v and w) or (t and v and not w and x) or
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(q and v and w and not x) or (x and not v);
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bcd(0) := y;
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return bcd;
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end;
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begin
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logical_0: process(all)
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variable rb_adj, rs_adj : std_ulogic_vector(63 downto 0);
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variable tmp : std_ulogic_vector(63 downto 0);
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variable negative : std_ulogic;
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variable j : integer;
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begin
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-- parity calculations
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par0 <= rs(0) xor rs(8) xor rs(16) xor rs(24);
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par1 <= rs(32) xor rs(40) xor rs(48) xor rs(56);
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parity <= (others => '0');
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if datalen(3) = '1' then
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parity(0) <= par0 xor par1;
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else
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parity(0) <= par0;
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parity(32) <= par1;
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end if;
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-- bit permutation
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for i in 0 to 7 loop
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j := i * 8;
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if rs(j+7 downto j+6) = "00" then
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permute(i) <= rb(to_integer(unsigned(not rs(j+5 downto j))));
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else
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permute(i) <= '0';
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end if;
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end loop;
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rb_adj := rb;
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if invert_in = '1' then
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rb_adj := not rb;
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end if;
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case op is
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when OP_LOGIC =>
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-- for now, abuse the 'is_signed' field to indicate inversion of RS
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rs_adj := rs;
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if is_signed = '1' then
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rs_adj := not rs;
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end if;
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tmp := rs_adj and rb_adj;
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if invert_out = '1' then
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tmp := not tmp;
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end if;
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when OP_XOR =>
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tmp := rs xor rb;
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if invert_out = '1' then
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tmp := not tmp;
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end if;
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when OP_BREV =>
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if datalen(3) = '1' then
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tmp := rs( 7 downto 0) & rs(15 downto 8) & rs(23 downto 16) & rs(31 downto 24) &
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rs(39 downto 32) & rs(47 downto 40) & rs(55 downto 48) & rs(63 downto 56);
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elsif datalen(2) = '1' then
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tmp := rs(39 downto 32) & rs(47 downto 40) & rs(55 downto 48) & rs(63 downto 56) &
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rs( 7 downto 0) & rs(15 downto 8) & rs(23 downto 16) & rs(31 downto 24);
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else
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tmp := rs(55 downto 48) & rs(63 downto 56) & rs(39 downto 32) & rs(47 downto 40) &
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rs(23 downto 16) & rs(31 downto 24) & rs( 7 downto 0) & rs(15 downto 8);
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end if;
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when OP_PRTY =>
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tmp := parity;
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when OP_CMPB =>
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tmp := ppc_cmpb(rs, rb);
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when OP_BPERM =>
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tmp := std_ulogic_vector(resize(unsigned(permute), 64));
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when OP_BCD =>
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-- invert_in is abused to indicate direction of conversion
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if invert_in = '0' then
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-- cbcdtd
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tmp := x"000" & bcd_to_dpd(rs(55 downto 44)) & bcd_to_dpd(rs(43 downto 32)) &
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x"000" & bcd_to_dpd(rs(23 downto 12)) & bcd_to_dpd(rs(11 downto 0));
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else
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-- cdtbcd
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tmp := x"00" & dpd_to_bcd(rs(51 downto 42)) & dpd_to_bcd(rs(41 downto 32)) &
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x"00" & dpd_to_bcd(rs(19 downto 10)) & dpd_to_bcd(rs(9 downto 0));
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end if;
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when OP_EXTS =>
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-- note datalen is a 1-hot encoding
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negative := (datalen(0) and rs(7)) or
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(datalen(1) and rs(15)) or
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(datalen(2) and rs(31));
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tmp := (others => negative);
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if datalen(2) = '1' then
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tmp(31 downto 16) := rs(31 downto 16);
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end if;
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if datalen(2) = '1' or datalen(1) = '1' then
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tmp(15 downto 8) := rs(15 downto 8);
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end if;
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tmp(7 downto 0) := rs(7 downto 0);
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when others =>
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-- e.g. OP_MFSPR
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tmp := rs;
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end case;
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result <= tmp;
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end process;
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end behaviour;
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