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119 lines
2.9 KiB
VHDL
119 lines
2.9 KiB
VHDL
library vunit_lib;
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context vunit_lib.vunit_context;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.wishbone_types.all;
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entity plru_tb is
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generic (runner_cfg : string := runner_cfg_default);
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end plru_tb;
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architecture behave of plru_tb is
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signal clk : std_ulogic;
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signal rst : std_ulogic;
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constant clk_period : time := 10 ns;
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constant plru_bits : integer := 3;
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subtype plru_val_t is std_ulogic_vector(plru_bits - 1 downto 0);
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subtype plru_tree_t is std_ulogic_vector(2 ** plru_bits - 2 downto 0);
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signal do_update : std_ulogic := '0';
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signal acc : plru_val_t;
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signal lru : plru_val_t;
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signal state : plru_tree_t;
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signal state_upd : plru_tree_t;
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begin
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plrufn0: entity work.plrufn
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generic map(
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BITS => plru_bits
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)
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port map(
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acc => acc,
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tree_in => state,
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tree_out => state_upd,
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lru => lru
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);
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clk_process: process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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rst_process: process
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begin
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rst <= '1';
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wait for 2*clk_period;
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rst <= '0';
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wait;
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end process;
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plru_process: process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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state <= (others => '0');
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elsif do_update = '1' then
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state <= state_upd;
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end if;
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end if;
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end process;
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stim_process: process
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procedure test_access(acc_val: integer; expected: integer) is
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begin
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acc <= std_ulogic_vector(to_unsigned(acc_val, acc'length));
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do_update <= '1';
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wait for clk_period;
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info("accessed " & integer'image(acc_val) & " LRU=" & to_hstring(lru));
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check_equal(lru, expected, result("LRU ACC=" & integer'image(acc_val)));
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end procedure;
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begin
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test_runner_setup(runner, runner_cfg);
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wait for 8*clk_period;
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info("reset state:" & to_hstring(lru));
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check_equal(lru, 0, result("LRU "));
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test_access(1, 4);
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test_access(2, 4);
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test_access(7, 0);
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test_access(4, 0);
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test_access(3, 6);
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test_access(5, 0);
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test_access(3, 6);
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test_access(5, 0);
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test_access(6, 0);
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test_access(0, 4);
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test_access(1, 4);
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test_access(2, 4);
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test_access(3, 4);
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test_access(4, 0);
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test_access(5, 0);
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test_access(6, 0);
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test_access(7, 0);
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test_access(6, 0);
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test_access(5, 0);
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test_access(4, 0);
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test_access(3, 7);
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test_access(2, 7);
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test_access(1, 7);
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test_access(0, 7);
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wait for clk_period;
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wait for clk_period;
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test_runner_cleanup(runner);
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end process;
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end;
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