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546 lines
18 KiB
VHDL
546 lines
18 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.wishbone_types.all;
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entity core is
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generic (
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SIM : boolean := false;
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DISABLE_FLATTEN : boolean := false;
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EX1_BYPASS : boolean := true;
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HAS_FPU : boolean := true;
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HAS_BTC : boolean := true;
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HAS_SHORT_MULT : boolean := false;
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ALT_RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0');
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LOG_LENGTH : natural := 512;
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ICACHE_NUM_LINES : natural := 64;
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ICACHE_NUM_WAYS : natural := 2;
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ICACHE_TLB_SIZE : natural := 64;
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DCACHE_NUM_LINES : natural := 64;
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DCACHE_NUM_WAYS : natural := 2;
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DCACHE_TLB_SET_SIZE : natural := 64;
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DCACHE_TLB_NUM_WAYS : natural := 2
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);
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port (
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clk : in std_ulogic;
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rst : in std_ulogic;
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-- Alternate reset (0xffff0000) for use by DRAM init fw
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alt_reset : in std_ulogic;
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-- Wishbone interface
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wishbone_insn_in : in wishbone_slave_out;
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wishbone_insn_out : out wishbone_master_out;
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wishbone_data_in : in wishbone_slave_out;
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wishbone_data_out : out wishbone_master_out;
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wb_snoop_in : in wishbone_master_out;
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dmi_addr : in std_ulogic_vector(3 downto 0);
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dmi_din : in std_ulogic_vector(63 downto 0);
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dmi_dout : out std_ulogic_vector(63 downto 0);
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dmi_req : in std_ulogic;
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dmi_wr : in std_ulogic;
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dmi_ack : out std_ulogic;
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ext_irq : in std_ulogic;
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terminated_out : out std_logic
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);
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end core;
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architecture behave of core is
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-- icache signals
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signal fetch1_to_icache : Fetch1ToIcacheType;
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signal writeback_to_fetch1: WritebackToFetch1Type;
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signal icache_to_decode1 : IcacheToDecode1Type;
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signal mmu_to_icache : MmuToIcacheType;
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-- decode signals
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signal decode1_to_decode2: Decode1ToDecode2Type;
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signal decode1_to_fetch1: Decode1ToFetch1Type;
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signal decode1_to_register_file: Decode1ToRegisterFileType;
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signal decode2_to_execute1: Decode2ToExecute1Type;
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-- register file signals
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signal register_file_to_decode2: RegisterFileToDecode2Type;
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signal decode2_to_register_file: Decode2ToRegisterFileType;
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signal writeback_to_register_file: WritebackToRegisterFileType;
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-- CR file signals
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signal decode2_to_cr_file: Decode2ToCrFileType;
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signal cr_file_to_decode2: CrFileToDecode2Type;
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signal writeback_to_cr_file: WritebackToCrFileType;
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-- execute signals
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signal execute1_to_writeback: Execute1ToWritebackType;
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signal execute1_bypass: bypass_data_t;
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signal execute1_cr_bypass: cr_bypass_data_t;
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signal execute2_bypass: bypass_data_t;
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signal execute2_cr_bypass: cr_bypass_data_t;
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-- load store signals
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signal execute1_to_loadstore1: Execute1ToLoadstore1Type;
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signal loadstore1_to_execute1: Loadstore1ToExecute1Type;
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signal loadstore1_to_writeback: Loadstore1ToWritebackType;
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signal loadstore1_to_mmu: Loadstore1ToMmuType;
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signal mmu_to_loadstore1: MmuToLoadstore1Type;
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-- dcache signals
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signal loadstore1_to_dcache: Loadstore1ToDcacheType;
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signal dcache_to_loadstore1: DcacheToLoadstore1Type;
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signal mmu_to_dcache: MmuToDcacheType;
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signal dcache_to_mmu: DcacheToMmuType;
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-- FPU signals
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signal execute1_to_fpu: Execute1ToFPUType;
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signal fpu_to_execute1: FPUToExecute1Type;
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signal fpu_to_writeback: FPUToWritebackType;
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-- Writeback signals
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signal writeback_bypass: bypass_data_t;
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signal wb_interrupt: WritebackToExecute1Type;
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-- local signals
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signal fetch1_stall_in : std_ulogic;
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signal icache_stall_out : std_ulogic;
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signal icache_stall_in : std_ulogic;
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signal decode1_stall_in : std_ulogic;
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signal decode1_busy : std_ulogic;
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signal decode2_busy_in : std_ulogic;
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signal decode2_stall_out : std_ulogic;
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signal ex1_icache_inval: std_ulogic;
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signal ex1_busy_out: std_ulogic;
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signal dcache_stall_out: std_ulogic;
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signal flush: std_ulogic;
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signal decode1_flush: std_ulogic;
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signal fetch1_flush: std_ulogic;
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signal complete: instr_tag_t;
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signal terminate: std_ulogic;
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signal core_rst: std_ulogic;
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-- Delayed/Latched resets and alt_reset
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signal rst_fetch1 : std_ulogic;
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signal rst_fetch2 : std_ulogic;
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signal rst_icache : std_ulogic;
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signal rst_dcache : std_ulogic;
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signal rst_dec1 : std_ulogic;
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signal rst_dec2 : std_ulogic;
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signal rst_ex1 : std_ulogic;
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signal rst_fpu : std_ulogic;
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signal rst_ls1 : std_ulogic;
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signal rst_wback : std_ulogic;
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signal rst_dbg : std_ulogic;
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signal alt_reset_d : std_ulogic;
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signal sim_ex_dump: std_ulogic;
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signal sim_cr_dump: std_ulogic;
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-- Debug actions
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signal dbg_core_stop: std_ulogic;
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signal dbg_core_rst: std_ulogic;
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signal dbg_icache_rst: std_ulogic;
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signal dbg_gpr_req : std_ulogic;
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signal dbg_gpr_ack : std_ulogic;
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signal dbg_gpr_addr : gspr_index_t;
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signal dbg_gpr_data : std_ulogic_vector(63 downto 0);
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signal dbg_spr_req : std_ulogic;
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signal dbg_spr_ack : std_ulogic;
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signal dbg_spr_addr : std_ulogic_vector(7 downto 0);
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signal dbg_spr_data : std_ulogic_vector(63 downto 0);
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signal dbg_ls_spr_req : std_ulogic;
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signal dbg_ls_spr_ack : std_ulogic;
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signal dbg_ls_spr_addr : std_ulogic_vector(1 downto 0);
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signal dbg_ls_spr_data : std_ulogic_vector(63 downto 0);
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signal ctrl_debug : ctrl_t;
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-- PMU event bus
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signal icache_events : IcacheEventType;
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signal loadstore_events : Loadstore1EventType;
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signal dcache_events : DcacheEventType;
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signal writeback_events : WritebackEventType;
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-- Debug status
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signal dbg_core_is_stopped: std_ulogic;
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-- Logging signals
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signal log_data : std_ulogic_vector(255 downto 0);
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signal log_rd_addr : std_ulogic_vector(31 downto 0);
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signal log_wr_addr : std_ulogic_vector(31 downto 0);
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signal log_rd_data : std_ulogic_vector(63 downto 0);
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function keep_h(disable : boolean) return string is
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begin
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if disable then
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return "yes";
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else
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return "no";
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end if;
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end function;
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attribute keep_hierarchy : string;
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attribute keep_hierarchy of fetch1_0 : label is keep_h(DISABLE_FLATTEN);
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attribute keep_hierarchy of icache_0 : label is keep_h(DISABLE_FLATTEN);
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attribute keep_hierarchy of decode1_0 : label is keep_h(DISABLE_FLATTEN);
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attribute keep_hierarchy of decode2_0 : label is keep_h(DISABLE_FLATTEN);
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attribute keep_hierarchy of register_file_0 : label is keep_h(DISABLE_FLATTEN);
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attribute keep_hierarchy of cr_file_0 : label is keep_h(DISABLE_FLATTEN);
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attribute keep_hierarchy of execute1_0 : label is keep_h(DISABLE_FLATTEN);
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attribute keep_hierarchy of loadstore1_0 : label is keep_h(DISABLE_FLATTEN);
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attribute keep_hierarchy of mmu_0 : label is keep_h(DISABLE_FLATTEN);
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attribute keep_hierarchy of dcache_0 : label is keep_h(DISABLE_FLATTEN);
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attribute keep_hierarchy of writeback_0 : label is keep_h(DISABLE_FLATTEN);
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attribute keep_hierarchy of debug_0 : label is keep_h(DISABLE_FLATTEN);
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begin
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core_rst <= dbg_core_rst or rst;
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resets: process(clk)
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begin
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if rising_edge(clk) then
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rst_fetch1 <= core_rst;
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rst_fetch2 <= core_rst;
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rst_icache <= core_rst;
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rst_dcache <= core_rst;
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rst_dec1 <= core_rst;
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rst_dec2 <= core_rst;
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rst_ex1 <= core_rst;
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rst_fpu <= core_rst;
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rst_ls1 <= core_rst;
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rst_wback <= core_rst;
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rst_dbg <= rst;
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alt_reset_d <= alt_reset;
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end if;
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end process;
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fetch1_0: entity work.fetch1
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generic map (
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RESET_ADDRESS => (others => '0'),
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ALT_RESET_ADDRESS => ALT_RESET_ADDRESS,
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HAS_BTC => HAS_BTC
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)
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port map (
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clk => clk,
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rst => rst_fetch1,
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alt_reset_in => alt_reset_d,
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stall_in => fetch1_stall_in,
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flush_in => fetch1_flush,
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inval_btc => ex1_icache_inval or mmu_to_icache.tlbie,
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stop_in => dbg_core_stop,
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d_in => decode1_to_fetch1,
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w_in => writeback_to_fetch1,
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i_out => fetch1_to_icache,
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log_out => log_data(42 downto 0)
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);
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fetch1_stall_in <= icache_stall_out or decode1_busy;
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fetch1_flush <= flush or decode1_flush;
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icache_0: entity work.icache
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generic map(
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SIM => SIM,
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HAS_FPU => HAS_FPU,
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LINE_SIZE => 64,
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NUM_LINES => ICACHE_NUM_LINES,
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NUM_WAYS => ICACHE_NUM_WAYS,
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TLB_SIZE => ICACHE_TLB_SIZE,
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LOG_LENGTH => LOG_LENGTH
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)
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port map(
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clk => clk,
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rst => rst_icache,
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i_in => fetch1_to_icache,
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i_out => icache_to_decode1,
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m_in => mmu_to_icache,
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flush_in => fetch1_flush,
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inval_in => dbg_icache_rst or ex1_icache_inval,
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stall_in => icache_stall_in,
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stall_out => icache_stall_out,
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wishbone_out => wishbone_insn_out,
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wishbone_in => wishbone_insn_in,
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wb_snoop_in => wb_snoop_in,
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events => icache_events,
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log_out => log_data(96 downto 43)
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);
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icache_stall_in <= decode1_busy;
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decode1_0: entity work.decode1
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generic map(
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HAS_FPU => HAS_FPU,
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LOG_LENGTH => LOG_LENGTH
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)
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port map (
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clk => clk,
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rst => rst_dec1,
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stall_in => decode1_stall_in,
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flush_in => flush,
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flush_out => decode1_flush,
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busy_out => decode1_busy,
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f_in => icache_to_decode1,
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d_out => decode1_to_decode2,
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f_out => decode1_to_fetch1,
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r_out => decode1_to_register_file,
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log_out => log_data(109 downto 97)
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);
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decode1_stall_in <= decode2_stall_out;
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decode2_0: entity work.decode2
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generic map (
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EX1_BYPASS => EX1_BYPASS,
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HAS_FPU => HAS_FPU,
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LOG_LENGTH => LOG_LENGTH
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)
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port map (
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clk => clk,
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rst => rst_dec2,
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busy_in => decode2_busy_in,
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stall_out => decode2_stall_out,
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flush_in => flush,
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complete_in => complete,
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stopped_out => dbg_core_is_stopped,
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d_in => decode1_to_decode2,
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e_out => decode2_to_execute1,
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r_in => register_file_to_decode2,
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r_out => decode2_to_register_file,
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c_in => cr_file_to_decode2,
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c_out => decode2_to_cr_file,
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execute_bypass => execute1_bypass,
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execute_cr_bypass => execute1_cr_bypass,
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execute2_bypass => execute2_bypass,
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execute2_cr_bypass => execute2_cr_bypass,
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writeback_bypass => writeback_bypass,
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dbg_spr_req => dbg_spr_req,
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dbg_spr_addr => dbg_spr_addr,
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log_out => log_data(119 downto 110)
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);
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decode2_busy_in <= ex1_busy_out;
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register_file_0: entity work.register_file
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generic map (
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SIM => SIM,
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HAS_FPU => HAS_FPU,
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LOG_LENGTH => LOG_LENGTH
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)
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port map (
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clk => clk,
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stall => decode2_stall_out,
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d1_in => decode1_to_register_file,
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d_in => decode2_to_register_file,
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d_out => register_file_to_decode2,
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w_in => writeback_to_register_file,
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dbg_gpr_req => dbg_gpr_req,
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dbg_gpr_ack => dbg_gpr_ack,
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dbg_gpr_addr => dbg_gpr_addr,
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dbg_gpr_data => dbg_gpr_data,
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sim_dump => terminate,
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sim_dump_done => sim_ex_dump,
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log_out => log_data(255 downto 184)
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);
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cr_file_0: entity work.cr_file
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generic map (
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SIM => SIM,
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LOG_LENGTH => LOG_LENGTH
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)
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port map (
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clk => clk,
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d_in => decode2_to_cr_file,
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d_out => cr_file_to_decode2,
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w_in => writeback_to_cr_file,
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sim_dump => sim_cr_dump,
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ctrl => ctrl_debug,
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log_out => log_data(183 downto 171)
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);
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execute1_0: entity work.execute1
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generic map (
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SIM => SIM,
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EX1_BYPASS => EX1_BYPASS,
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HAS_FPU => HAS_FPU,
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HAS_SHORT_MULT => HAS_SHORT_MULT,
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LOG_LENGTH => LOG_LENGTH
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)
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port map (
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clk => clk,
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rst => rst_ex1,
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flush_in => flush,
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busy_out => ex1_busy_out,
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e_in => decode2_to_execute1,
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l_in => loadstore1_to_execute1,
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fp_in => fpu_to_execute1,
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ext_irq_in => ext_irq,
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interrupt_in => wb_interrupt,
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l_out => execute1_to_loadstore1,
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fp_out => execute1_to_fpu,
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e_out => execute1_to_writeback,
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bypass_data => execute1_bypass,
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bypass_cr_data => execute1_cr_bypass,
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bypass2_data => execute2_bypass,
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bypass2_cr_data => execute2_cr_bypass,
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icache_inval => ex1_icache_inval,
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dbg_ctrl_out => ctrl_debug,
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wb_events => writeback_events,
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ls_events => loadstore_events,
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dc_events => dcache_events,
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ic_events => icache_events,
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terminate_out => terminate,
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dbg_spr_req => dbg_spr_req,
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dbg_spr_ack => dbg_spr_ack,
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dbg_spr_addr => dbg_spr_addr,
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dbg_spr_data => dbg_spr_data,
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sim_dump => sim_ex_dump,
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sim_dump_done => sim_cr_dump,
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log_out => log_data(134 downto 120),
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log_rd_addr => log_rd_addr,
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log_rd_data => log_rd_data,
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log_wr_addr => log_wr_addr
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);
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with_fpu: if HAS_FPU generate
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begin
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fpu_0: entity work.fpu
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port map (
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clk => clk,
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rst => rst_fpu,
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flush_in => flush,
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e_in => execute1_to_fpu,
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e_out => fpu_to_execute1,
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w_out => fpu_to_writeback
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);
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end generate;
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no_fpu: if not HAS_FPU generate
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begin
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fpu_to_execute1 <= FPUToExecute1Init;
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fpu_to_writeback <= FPUToWritebackInit;
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end generate;
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loadstore1_0: entity work.loadstore1
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generic map (
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HAS_FPU => HAS_FPU,
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LOG_LENGTH => LOG_LENGTH
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)
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port map (
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clk => clk,
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rst => rst_ls1,
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l_in => execute1_to_loadstore1,
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e_out => loadstore1_to_execute1,
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l_out => loadstore1_to_writeback,
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d_out => loadstore1_to_dcache,
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d_in => dcache_to_loadstore1,
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m_out => loadstore1_to_mmu,
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m_in => mmu_to_loadstore1,
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dc_stall => dcache_stall_out,
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events => loadstore_events,
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dbg_spr_req => dbg_ls_spr_req,
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dbg_spr_ack => dbg_ls_spr_ack,
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dbg_spr_addr => dbg_ls_spr_addr,
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dbg_spr_data => dbg_ls_spr_data,
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log_out => log_data(149 downto 140)
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);
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mmu_0: entity work.mmu
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port map (
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clk => clk,
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rst => core_rst,
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l_in => loadstore1_to_mmu,
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l_out => mmu_to_loadstore1,
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d_out => mmu_to_dcache,
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d_in => dcache_to_mmu,
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i_out => mmu_to_icache
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);
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dcache_0: entity work.dcache
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generic map(
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LINE_SIZE => 64,
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NUM_LINES => DCACHE_NUM_LINES,
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NUM_WAYS => DCACHE_NUM_WAYS,
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TLB_SET_SIZE => DCACHE_TLB_SET_SIZE,
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TLB_NUM_WAYS => DCACHE_TLB_NUM_WAYS,
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LOG_LENGTH => LOG_LENGTH
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)
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port map (
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clk => clk,
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rst => rst_dcache,
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d_in => loadstore1_to_dcache,
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d_out => dcache_to_loadstore1,
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m_in => mmu_to_dcache,
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m_out => dcache_to_mmu,
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|
stall_out => dcache_stall_out,
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|
wishbone_in => wishbone_data_in,
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wishbone_out => wishbone_data_out,
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snoop_in => wb_snoop_in,
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events => dcache_events,
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|
log_out => log_data(170 downto 151)
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);
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|
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writeback_0: entity work.writeback
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|
port map (
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|
clk => clk,
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rst => rst_wback,
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flush_out => flush,
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e_in => execute1_to_writeback,
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l_in => loadstore1_to_writeback,
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|
fp_in => fpu_to_writeback,
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|
w_out => writeback_to_register_file,
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|
c_out => writeback_to_cr_file,
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|
f_out => writeback_to_fetch1,
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|
wb_bypass => writeback_bypass,
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|
events => writeback_events,
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|
interrupt_out => wb_interrupt,
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|
complete_out => complete
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|
);
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|
|
|
log_data(150) <= '0';
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|
log_data(139 downto 135) <= "00000";
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|
|
|
debug_0: entity work.core_debug
|
|
generic map (
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|
LOG_LENGTH => LOG_LENGTH
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|
)
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|
port map (
|
|
clk => clk,
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|
rst => rst_dbg,
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|
dmi_addr => dmi_addr,
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|
dmi_din => dmi_din,
|
|
dmi_dout => dmi_dout,
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|
dmi_req => dmi_req,
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|
dmi_wr => dmi_wr,
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|
dmi_ack => dmi_ack,
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|
core_stop => dbg_core_stop,
|
|
core_rst => dbg_core_rst,
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|
icache_rst => dbg_icache_rst,
|
|
terminate => terminate,
|
|
core_stopped => dbg_core_is_stopped,
|
|
nia => fetch1_to_icache.nia,
|
|
msr => ctrl_debug.msr,
|
|
dbg_gpr_req => dbg_gpr_req,
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|
dbg_gpr_ack => dbg_gpr_ack,
|
|
dbg_gpr_addr => dbg_gpr_addr,
|
|
dbg_gpr_data => dbg_gpr_data,
|
|
dbg_spr_req => dbg_spr_req,
|
|
dbg_spr_ack => dbg_spr_ack,
|
|
dbg_spr_addr => dbg_spr_addr,
|
|
dbg_spr_data => dbg_spr_data,
|
|
dbg_ls_spr_req => dbg_ls_spr_req,
|
|
dbg_ls_spr_ack => dbg_ls_spr_ack,
|
|
dbg_ls_spr_addr => dbg_ls_spr_addr,
|
|
dbg_ls_spr_data => dbg_ls_spr_data,
|
|
log_data => log_data,
|
|
log_read_addr => log_rd_addr,
|
|
log_read_data => log_rd_data,
|
|
log_write_addr => log_wr_addr,
|
|
terminated_out => terminated_out
|
|
);
|
|
|
|
end behave;
|