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caravel-mpw7-20221125
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microwatt/litedram
History
Benjamin Herrenschmidt f9f18906a3 soc: Rename wb_dram_ctrl to wb_ext_io and rework decoding 
This makes the control bus currently going out of "soc" towards
litedram more generic for external IO devices added by the
top-level rather than inside the SoC proper.

This is mostly renaming of signals and a small change on how the
address decoder operates, using a separate "cascaded" decode for
the external IOs.

We make the region 0xc8nn_nnnn be the "external IO" region for
now.

This will make it easier / cleaner to add more external devices.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 		5 years ago
..
extras litedram: L2 use latched refill_index 5 years ago
gen-src spi: Add booting from flash to litedram init 5 years ago
generated soc: Rename wb_dram_ctrl to wb_ext_io and rework decoding 5 years ago
litedram.core litedram: Add basic support for LiteX LiteDRAM 5 years ago