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327 lines
11 KiB
VHDL
327 lines
11 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.common.all;
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entity control is
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generic (
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EX1_BYPASS : boolean := true;
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PIPELINE_DEPTH : natural := 3
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);
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port (
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clk : in std_ulogic;
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rst : in std_ulogic;
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complete_in : in instr_tag_t;
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valid_in : in std_ulogic;
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repeated : in std_ulogic;
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flush_in : in std_ulogic;
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busy_in : in std_ulogic;
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deferred : in std_ulogic;
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sgl_pipe_in : in std_ulogic;
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stop_mark_in : in std_ulogic;
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gpr_write_valid_in : in std_ulogic;
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gpr_write_in : in gspr_index_t;
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gpr_a_read_valid_in : in std_ulogic;
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gpr_a_read_in : in gspr_index_t;
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gpr_b_read_valid_in : in std_ulogic;
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gpr_b_read_in : in gspr_index_t;
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gpr_c_read_valid_in : in std_ulogic;
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gpr_c_read_in : in gspr_index_t;
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execute_next_tag : in instr_tag_t;
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execute_next_cr_tag : in instr_tag_t;
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cr_read_in : in std_ulogic;
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cr_write_in : in std_ulogic;
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valid_out : out std_ulogic;
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stall_out : out std_ulogic;
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stopped_out : out std_ulogic;
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gpr_bypass_a : out std_ulogic;
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gpr_bypass_b : out std_ulogic;
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gpr_bypass_c : out std_ulogic;
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cr_bypass : out std_ulogic;
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instr_tag_out : out instr_tag_t
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);
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end entity control;
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architecture rtl of control is
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type state_type is (IDLE, WAIT_FOR_PREV_TO_COMPLETE, WAIT_FOR_CURR_TO_COMPLETE);
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type reg_internal_type is record
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state : state_type;
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outstanding : integer range -1 to PIPELINE_DEPTH+2;
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end record;
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constant reg_internal_init : reg_internal_type := (state => IDLE, outstanding => 0);
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signal r_int, rin_int : reg_internal_type := reg_internal_init;
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signal gpr_write_valid : std_ulogic := '0';
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signal cr_write_valid : std_ulogic := '0';
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type tag_register is record
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wr_gpr : std_ulogic;
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reg : gspr_index_t;
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recent : std_ulogic;
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wr_cr : std_ulogic;
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end record;
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type tag_regs_array is array(tag_number_t) of tag_register;
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signal tag_regs : tag_regs_array;
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signal instr_tag : instr_tag_t;
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signal gpr_tag_stall : std_ulogic;
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signal cr_tag_stall : std_ulogic;
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signal curr_tag : tag_number_t;
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signal next_tag : tag_number_t;
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signal curr_cr_tag : tag_number_t;
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begin
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control0: process(clk)
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begin
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if rising_edge(clk) then
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assert rin_int.outstanding >= 0 and rin_int.outstanding <= (PIPELINE_DEPTH+1)
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report "Outstanding bad " & integer'image(rin_int.outstanding) severity failure;
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r_int <= rin_int;
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for i in tag_number_t loop
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if rst = '1' or flush_in = '1' then
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tag_regs(i).wr_gpr <= '0';
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tag_regs(i).wr_cr <= '0';
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else
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if complete_in.valid = '1' and i = complete_in.tag then
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tag_regs(i).wr_gpr <= '0';
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tag_regs(i).wr_cr <= '0';
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report "tag " & integer'image(i) & " not valid";
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end if;
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if gpr_write_valid = '1' and tag_regs(i).reg = gpr_write_in then
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tag_regs(i).recent <= '0';
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if tag_regs(i).recent = '1' and tag_regs(i).wr_gpr = '1' then
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report "tag " & integer'image(i) & " not recent";
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end if;
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end if;
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if instr_tag.valid = '1' and i = instr_tag.tag then
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tag_regs(i).wr_gpr <= gpr_write_valid;
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tag_regs(i).reg <= gpr_write_in;
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tag_regs(i).recent <= gpr_write_valid;
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tag_regs(i).wr_cr <= cr_write_valid;
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if gpr_write_valid = '1' then
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report "tag " & integer'image(i) & " valid for gpr " & to_hstring(gpr_write_in);
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end if;
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end if;
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end if;
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end loop;
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if rst = '1' then
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curr_tag <= 0;
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curr_cr_tag <= 0;
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else
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curr_tag <= next_tag;
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if cr_write_valid = '1' then
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curr_cr_tag <= instr_tag.tag;
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end if;
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end if;
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end if;
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end process;
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control_hazards : process(all)
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variable gpr_stall : std_ulogic;
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variable tag_a : instr_tag_t;
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variable tag_b : instr_tag_t;
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variable tag_c : instr_tag_t;
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variable tag_s : instr_tag_t;
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variable tag_t : instr_tag_t;
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variable incr_tag : tag_number_t;
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variable byp_a : std_ulogic;
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variable byp_b : std_ulogic;
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variable byp_c : std_ulogic;
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variable tag_cr : instr_tag_t;
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variable byp_cr : std_ulogic;
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begin
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tag_a := instr_tag_init;
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for i in tag_number_t loop
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if tag_regs(i).wr_gpr = '1' and tag_regs(i).recent = '1' and tag_regs(i).reg = gpr_a_read_in then
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tag_a.valid := gpr_a_read_valid_in;
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tag_a.tag := i;
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end if;
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end loop;
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if tag_match(tag_a, complete_in) then
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tag_a.valid := '0';
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end if;
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tag_b := instr_tag_init;
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for i in tag_number_t loop
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if tag_regs(i).wr_gpr = '1' and tag_regs(i).recent = '1' and tag_regs(i).reg = gpr_b_read_in then
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tag_b.valid := gpr_b_read_valid_in;
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tag_b.tag := i;
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end if;
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end loop;
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if tag_match(tag_b, complete_in) then
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tag_b.valid := '0';
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end if;
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tag_c := instr_tag_init;
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for i in tag_number_t loop
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if tag_regs(i).wr_gpr = '1' and tag_regs(i).recent = '1' and tag_regs(i).reg = gpr_c_read_in then
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tag_c.valid := gpr_c_read_valid_in;
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tag_c.tag := i;
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end if;
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end loop;
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if tag_match(tag_c, complete_in) then
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tag_c.valid := '0';
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end if;
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byp_a := '0';
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if EX1_BYPASS and tag_match(execute_next_tag, tag_a) then
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byp_a := '1';
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end if;
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byp_b := '0';
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if EX1_BYPASS and tag_match(execute_next_tag, tag_b) then
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byp_b := '1';
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end if;
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byp_c := '0';
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if EX1_BYPASS and tag_match(execute_next_tag, tag_c) then
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byp_c := '1';
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end if;
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gpr_bypass_a <= byp_a;
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gpr_bypass_b <= byp_b;
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gpr_bypass_c <= byp_c;
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gpr_tag_stall <= (tag_a.valid and not byp_a) or
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(tag_b.valid and not byp_b) or
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(tag_c.valid and not byp_c);
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incr_tag := curr_tag;
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instr_tag.tag <= curr_tag;
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instr_tag.valid <= valid_out and not deferred;
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if instr_tag.valid = '1' then
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incr_tag := (curr_tag + 1) mod TAG_COUNT;
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end if;
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next_tag <= incr_tag;
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instr_tag_out <= instr_tag;
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-- CR hazards
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tag_cr.tag := curr_cr_tag;
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tag_cr.valid := cr_read_in and tag_regs(curr_cr_tag).wr_cr;
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if tag_match(tag_cr, complete_in) then
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tag_cr.valid := '0';
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end if;
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byp_cr := '0';
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if EX1_BYPASS and tag_match(execute_next_cr_tag, tag_cr) then
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byp_cr := '1';
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end if;
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cr_bypass <= byp_cr;
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cr_tag_stall <= tag_cr.valid and not byp_cr;
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end process;
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control1 : process(all)
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variable v_int : reg_internal_type;
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variable valid_tmp : std_ulogic;
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variable stall_tmp : std_ulogic;
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begin
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v_int := r_int;
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-- asynchronous
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valid_tmp := valid_in and not flush_in;
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stall_tmp := '0';
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if flush_in = '1' then
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v_int.outstanding := 0;
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elsif complete_in.valid = '1' then
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v_int.outstanding := r_int.outstanding - 1;
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end if;
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if r_int.outstanding >= PIPELINE_DEPTH + 1 then
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valid_tmp := '0';
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stall_tmp := '1';
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end if;
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if rst = '1' then
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v_int := reg_internal_init;
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valid_tmp := '0';
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end if;
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-- Handle debugger stop
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stopped_out <= '0';
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if stop_mark_in = '1' and v_int.outstanding = 0 then
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stopped_out <= '1';
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end if;
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-- state machine to handle instructions that must be single
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-- through the pipeline.
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case r_int.state is
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when IDLE =>
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if valid_tmp = '1' then
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if (sgl_pipe_in = '1') then
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if v_int.outstanding /= 0 then
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v_int.state := WAIT_FOR_PREV_TO_COMPLETE;
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stall_tmp := '1';
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else
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-- send insn out and wait on it to complete
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v_int.state := WAIT_FOR_CURR_TO_COMPLETE;
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end if;
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else
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-- let it go out if there are no GPR or CR hazards
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stall_tmp := gpr_tag_stall or cr_tag_stall;
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end if;
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end if;
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when WAIT_FOR_PREV_TO_COMPLETE =>
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if v_int.outstanding = 0 then
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-- send insn out and wait on it to complete
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v_int.state := WAIT_FOR_CURR_TO_COMPLETE;
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else
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stall_tmp := '1';
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end if;
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when WAIT_FOR_CURR_TO_COMPLETE =>
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if v_int.outstanding = 0 then
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v_int.state := IDLE;
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-- XXX Don't replicate this
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if valid_tmp = '1' then
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if (sgl_pipe_in = '1') then
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if v_int.outstanding /= 0 then
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v_int.state := WAIT_FOR_PREV_TO_COMPLETE;
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stall_tmp := '1';
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else
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-- send insn out and wait on it to complete
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v_int.state := WAIT_FOR_CURR_TO_COMPLETE;
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end if;
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else
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-- let it go out if there are no GPR or CR hazards
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stall_tmp := gpr_tag_stall or cr_tag_stall;
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end if;
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end if;
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else
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stall_tmp := '1';
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end if;
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end case;
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if stall_tmp = '1' then
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valid_tmp := '0';
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end if;
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gpr_write_valid <= gpr_write_valid_in and valid_tmp;
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cr_write_valid <= cr_write_in and valid_tmp;
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if valid_tmp = '1' and deferred = '0' then
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v_int.outstanding := v_int.outstanding + 1;
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end if;
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-- update outputs
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valid_out <= valid_tmp;
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stall_out <= stall_tmp or deferred;
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-- update registers
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rin_int <= v_int;
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end process;
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end;
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