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Anton Blanchard 61d5e61f09 Add a few FFs on the RX input to avoid metastability issues ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>		5 years ago
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LICENSE	…
arty_a7.xdc	Add SPI configuration to Xilinx constraint files	5 years ago
clk_gen_bypass.vhd	Fix clk_gen_bypass	5 years ago
clk_gen_mcmm.vhd	Improve PLL/MMCM clocks configuration	5 years ago
clk_gen_plle2.vhd	Improve PLL/MMCM clocks configuration	5 years ago
cmod_a7-35.xdc	Add SPI configuration to Xilinx constraint files	5 years ago
firmware.hex	…
hello_world.hex	Rebuild hello world assuming a 50MHz clock	5 years ago
main_bram.vhdl	Fix some ghdlsynth issues with fpga_bram	5 years ago
nexys-video.xdc	Add SPI configuration to Xilinx constraint files	5 years ago
nexys_a7.xdc	Add SPI configuration to Xilinx constraint files	5 years ago
pp_fifo.vhd	fifo: Reformat	5 years ago
pp_soc_uart.vhd	Add a few FFs on the RX input to avoid metastability issues	5 years ago
pp_utilities.vhd	…
soc_reset.vhdl	Rework SOC reset	5 years ago
soc_reset_tb.vhdl	Rework SOC reset	5 years ago
toplevel.vhdl	Reduce simulated and default FPGA RAM to 384kB	5 years ago