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Benjamin Herrenschmidt 39c2abae51 Fix build of core_dram_tb and dram_tb and fix tracing ... We disabled --trace by default, so we need to stop linking verilated_vcd_c.o as it doesn't exist in that case. While at it, make a Makefile variable to enable/disable verilator tracing and add a couple of generics to those test benches to control tracing in the L2 and in litedram. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		2 years ago
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fusesoc-add-files.py	litedram: Remove old "VexRiscV" based initializations	5 years ago
litedram-wrapper-l2.vhdl	Extend LiteDRAM VHDL wrapper to allow more than one clock line	3 years ago
sim_dram_verilate.mk	litedram: Add simulation support	5 years ago
sim_litedram.vhdl	Extend LiteDRAM VHDL wrapper to allow more than one clock line	3 years ago
sim_litedram_c.cpp	Fix build of core_dram_tb and dram_tb and fix tracing	2 years ago
wave.gtkw	litedram: Add an L2 cache with store queue	5 years ago
wave.opt	litedram: Add an L2 cache with store queue	5 years ago
wave_tb.gtkw	litedram: l2: Latency improvements	4 years ago