With the multiply-add instructions, it is possible to get into state
FMADD_6 with R containing a value >= 8.0. If the value is exactly
8.0, the logic will incorrectly conclude that the result is zero
because it only tests bits up to UNIT_BIT + 2. Fix this by testing
up to UNIT_BIT + 3, and add a test case to the FPU test that triggers
this situation.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>