A tiny Open POWER ISA softcore written in VHDL 2008
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Paul Mackerras 4396eddc31 countzero: Add a testbench
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
fpga Fix clk_gen_bypass 5 years ago
hello_world Rebuild hello world assuming a 50MHz clock 5 years ago
media Add title image 5 years ago
scripts New C based JTAG debug tool 5 years ago
sim-unisim Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs 5 years ago
tests Initial import of microwatt 5 years ago
.gitignore Update gitignore for new test bench build files 5 years ago
.travis.yml Allow a full make check on Travis 5 years ago
LICENSE Initial import of microwatt 5 years ago
Makefile countzero: Add a testbench 5 years ago
README.md Add logo to README.md 5 years ago
cache_ram.vhdl icache: Set associative icache 5 years ago
common.vhdl Merge pull request #81 from antonblanchard/logical 5 years ago
core.vhdl divider: Return 0 for invalid and overflow cases, like P9 does 5 years ago
core_debug.vhdl fetch/icache: Fit icache in BRAM 5 years ago
core_tb.vhdl Add core debug module 5 years ago
countzero.vhdl countzero: Reorganize to have fewer levels of logic and fewer LUTs 5 years ago
countzero_tb.vhdl countzero: Add a testbench 5 years ago
cr_file.vhdl Reformat CR file 5 years ago
crhelpers.vhdl Reformat crhelpers, and remove some stale code 5 years ago
decode1.vhdl mod* doesn't have an RC form 5 years ago
decode2.vhdl decode2: Fix 32-bit flag passed to divider 5 years ago
decode_types.vhdl execute: Consolidate count-leading/trailing-zeroes implementations 5 years ago
divider.vhdl divider: Return 0 for invalid and overflow cases, like P9 does 5 years ago
divider_tb.vhdl divider: Return 0 for invalid and overflow cases, like P9 does 5 years ago
dmi_dtm_dummy.vhdl Fix build issue in dmi_dtm_dummy.vhdl 5 years ago
dmi_dtm_tb.vhdl Wishbone debug module 5 years ago
dmi_dtm_xilinx.vhdl Don't reset JTAG request register asynchronously 5 years ago
execute1.vhdl Don't infer latch for newcrf 5 years ago
execute2.vhdl Reformat execute2 5 years ago
fetch1.vhdl fetch/icache: Fit icache in BRAM 5 years ago
fetch2.vhdl fetch2: Remove blank line 5 years ago
glibc_random.vhdl Reformat glibc_random 5 years ago
glibc_random_helpers.vhdl Reformat glibc_random 5 years ago
helpers.vhdl Reformat helpers 5 years ago
icache.vhdl icache: Set associative icache 5 years ago
icache_tb.vhdl icache: Use narrower block RAMs 5 years ago
insn_helpers.vhdl Add MCRF instruction 5 years ago
loadstore1.vhdl Reformat loadstore1 5 years ago
loadstore2.vhdl loadstore2: Do data formatting after a register stage 5 years ago
logical.vhdl Consolidate logical instructions 5 years ago
microwatt.core Fix cmod-a7 frequency 5 years ago
multiply.vhdl Multiply needs to be 16 stages to fix all timing issues 5 years ago
multiply_tb.vhdl Reformat multiply_tb 5 years ago
plru.vhdl icache: Set associative icache 5 years ago
plru_tb.vhdl plru: Add a simple PLRU module 5 years ago
ppc_fx_insns.vhdl Implement absolute branches 5 years ago
register_file.vhdl Fix register file size (there are 32 gprs). 5 years ago
rotator.vhdl Add a rotate/mask/shift unit and use it in execute1 5 years ago
rotator_tb.vhdl Add a rotate/mask/shift unit and use it in execute1 5 years ago
sim_console.vhdl Reformat sim_console 5 years ago
sim_console_c.c Make sim poll non-blocking 5 years ago
sim_jtag.vhdl Add jtag support in simulation via a socket 5 years ago
sim_jtag_socket.vhdl Add jtag support in simulation via a socket 5 years ago
sim_jtag_socket_c.c debug/sim: Make connect/disconnect messages quieter 5 years ago
sim_uart.vhdl Share soc.vhdl between FPGA and sim 5 years ago
simple_ram_behavioural.vhdl Reformat simple_ram_behavioural 5 years ago
simple_ram_behavioural_helpers.vhdl Reformat simple_ram_behavioural 5 years ago
simple_ram_behavioural_helpers_c.c Silence some loadstore related debug 5 years ago
simple_ram_behavioural_tb.bin Initial import of microwatt 5 years ago
simple_ram_behavioural_tb.vhdl Reformat simple_ram_behavioural 5 years ago
soc.vhdl Tighten UART address 5 years ago
wishbone_arbiter.vhdl Use a 3 way WB arbiter and cleanup fpga toplevel 5 years ago
wishbone_debug_master.vhdl Wishbone debug module 5 years ago
wishbone_types.vhdl Reformat wishbone code 5 years ago
writeback.vhdl Add a divider unit and a testbench for it 5 years ago

README.md

Microwatt

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

  • Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com
git clone https://github.com/mikey/micropython
cd micropython
git checkout powerpc
cd ports/powerpc
make -j$(nproc)
cd ../../../
  • Microwatt uses ghdl for simulation. Either install this from your distro or build it. Next build microwatt:
git clone https://github.com/antonblanchard/microwatt
cd microwatt
make
  • Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin simple_ram_behavioural.bin
  • Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

  • Install Vivado (I'm using the free 2019.1 webpack edition).

  • Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh
  • Install FuseSoC:
pip3 install --user -U fusesoc
  • Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
  • Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board):
fusesoc run --target=nexys_video microwatt --memory_size=8192 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex
  • To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt

Testing

  • A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

  • There are a few instructions still to be implemented
  • Need to add caches and bypassing (in progress)
  • Need to add supervisor state (in progress)