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44 lines
1.2 KiB
Python
44 lines
1.2 KiB
Python
#!/usr/bin/env python3
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import json
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from pathlib import Path
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from vunit import VUnit
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ROOT = Path(__file__).parent
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PRJ = VUnit.from_argv()
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PRJ.add_osvvm()
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PRJ.add_library("lib").add_source_files([
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ROOT / "litedram" / "extras" / "*.vhdl",
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ROOT / "litedram" / "generated" / "sim" / "*.vhdl"
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] + [
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src_file
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for src_file in ROOT.glob("*.vhdl")
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# Use multiply.vhd and not xilinx-mult.vhd. Use VHDL-based random.
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if not any(exclude in str(src_file) for exclude in ["xilinx-mult", "foreign_random", "nonrandom", "dmi_dtm_ecp5", "dmi_dtm_xilinx"])
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])
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PRJ.add_library("unisim").add_source_files(ROOT / "sim-unisim" / "*.vhdl")
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PRJ.set_sim_option("disable_ieee_warnings", True)
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def _gen_vhdl_ls(vu):
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"""
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Generate the vhdl_ls.toml file required by VHDL-LS language server.
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"""
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# Repo root
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parent = Path(__file__).parent
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proj = vu._project
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libs = proj.get_libraries()
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with open(parent / 'vhdl_ls.toml', "w") as f:
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for lib in libs:
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f.write(f"[libraries.{lib.name}]\n")
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files = [str(file).replace('\\', '/') for file in lib._source_files]
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f.write(f"files = {json.dumps(files, indent=4)}\n")
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_gen_vhdl_ls(PRJ)
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PRJ.main()
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