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136 lines
4.6 KiB
VHDL
136 lines
4.6 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.decode_types.all;
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entity divider is
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port (
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clk : in std_logic;
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rst : in std_logic;
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d_in : in Execute1ToDividerType;
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d_out : out DividerToExecute1Type
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);
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end entity divider;
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architecture behaviour of divider is
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signal dend : std_ulogic_vector(128 downto 0);
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signal div : unsigned(63 downto 0);
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signal quot : std_ulogic_vector(63 downto 0);
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signal result : std_ulogic_vector(63 downto 0);
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signal sresult : std_ulogic_vector(64 downto 0);
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signal oresult : std_ulogic_vector(63 downto 0);
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signal running : std_ulogic;
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signal count : unsigned(6 downto 0);
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signal neg_result : std_ulogic;
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signal is_modulus : std_ulogic;
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signal is_32bit : std_ulogic;
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signal extended : std_ulogic;
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signal is_signed : std_ulogic;
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signal overflow : std_ulogic;
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signal ovf32 : std_ulogic;
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signal did_ovf : std_ulogic;
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begin
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divider_0: process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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dend <= (others => '0');
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div <= (others => '0');
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quot <= (others => '0');
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running <= '0';
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count <= "0000000";
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elsif d_in.valid = '1' then
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if d_in.is_extended = '1' then
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dend <= '0' & d_in.dividend & x"0000000000000000";
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else
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dend <= '0' & x"0000000000000000" & d_in.dividend;
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end if;
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div <= unsigned(d_in.divisor);
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quot <= (others => '0');
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neg_result <= d_in.neg_result;
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is_modulus <= d_in.is_modulus;
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extended <= d_in.is_extended;
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is_32bit <= d_in.is_32bit;
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is_signed <= d_in.is_signed;
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count <= "1111111";
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running <= '1';
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overflow <= '0';
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ovf32 <= '0';
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elsif running = '1' then
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if count = "0111111" then
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running <= '0';
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end if;
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overflow <= quot(63);
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if dend(128) = '1' or unsigned(dend(127 downto 64)) >= div then
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ovf32 <= ovf32 or quot(31);
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dend <= std_ulogic_vector(unsigned(dend(127 downto 64)) - div) &
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dend(63 downto 0) & '0';
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quot <= quot(62 downto 0) & '1';
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count <= count + 1;
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elsif dend(128 downto 57) = x"000000000000000000" and count(6 downto 3) /= "0111" then
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-- consume 8 bits of zeroes in one cycle
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ovf32 <= or (ovf32 & quot(31 downto 24));
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dend <= dend(120 downto 0) & x"00";
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quot <= quot(55 downto 0) & x"00";
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count <= count + 8;
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else
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ovf32 <= ovf32 or quot(31);
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dend <= dend(127 downto 0) & '0';
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quot <= quot(62 downto 0) & '0';
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count <= count + 1;
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end if;
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else
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count <= "0000000";
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end if;
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end if;
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end process;
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divider_1: process(all)
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begin
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if is_modulus = '1' then
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result <= dend(128 downto 65);
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else
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result <= quot;
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end if;
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if neg_result = '1' then
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sresult <= std_ulogic_vector(- signed('0' & result));
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else
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sresult <= '0' & result;
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end if;
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did_ovf <= '0';
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if is_32bit = '0' then
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did_ovf <= overflow or (is_signed and (sresult(64) xor sresult(63)));
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elsif is_signed = '1' then
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if ovf32 = '1' or sresult(32) /= sresult(31) then
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did_ovf <= '1';
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end if;
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else
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did_ovf <= ovf32;
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end if;
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if did_ovf = '1' then
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oresult <= (others => '0');
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elsif (is_32bit = '1') and (is_modulus = '0') then
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-- 32-bit divisions set the top 32 bits of the result to 0
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oresult <= x"00000000" & sresult(31 downto 0);
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else
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oresult <= sresult(63 downto 0);
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end if;
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end process;
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divider_out: process(clk)
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begin
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if rising_edge(clk) then
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d_out.valid <= '0';
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d_out.write_reg_data <= oresult;
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d_out.overflow <= did_ovf;
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if count = "1000000" then
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d_out.valid <= '1';
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end if;
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end if;
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end process;
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end architecture behaviour;
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