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187 lines
5.2 KiB
VHDL
187 lines
5.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package mc_pkg is
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constant BAR_BITS : integer := 16;
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--types
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type T_Config is record
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oib_en : std_ulogic;
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oib_ratio : std_ulogic_vector(3 downto 0);
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oib_width : std_ulogic_vector(2 downto 0);
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cpol : std_ulogic;
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cpha : std_ulogic;
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ib_en_pck : std_ulogic;
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rsvd0 : std_ulogic_vector(2 downto 0);
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bar_en : std_ulogic;
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int_req : std_ulogic;
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bar : std_ulogic_vector(BAR_BITS-1 downto 0);
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--bar mask
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rsvd1 : std_ulogic_vector(7 downto 0);
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idle_flit : std_ulogic_vector(7 downto 0);
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rcv_header : std_ulogic_vector(7 downto 0);
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err : std_ulogic_vector(7 downto 0);
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end record;
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-- functions
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function inc(a: in std_ulogic_vector) return std_ulogic_vector;
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function inc(a: in std_ulogic_vector; b: in integer) return std_ulogic_vector;use ieee.numeric_std.all;
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function dec(a: in std_ulogic_vector) return std_ulogic_vector;
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function eq(a: in std_ulogic_vector; b: in integer) return boolean;
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function eq(a: in std_ulogic_vector; b: in integer) return std_ulogic;
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function eq(a: in std_ulogic_vector; b: in std_ulogic_vector) return boolean;
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function eq(a: in std_ulogic_vector; b: in std_ulogic_vector) return std_ulogic;
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function gate_and(a: in std_ulogic; b: in std_ulogic_vector) return std_ulogic_vector;
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function or_reduce(slv: in std_ulogic_vector) return std_ulogic;
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function and_reduce(slv: in std_ulogic_vector) return std_ulogic;
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function clog2(n : in integer) return integer;
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function bus_ratio_enc(n : in integer) return std_ulogic_vector;
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function bus_width_enc(n : in integer) return std_ulogic_vector;
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end package mc_pkg;
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package body mc_pkg is
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function inc(a: in std_ulogic_vector) return std_ulogic_vector is
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variable res: std_ulogic_vector(0 to a'length-1);
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begin
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res := std_ulogic_vector(unsigned(a) + 1);
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return res;
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end function;
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function inc(a: in std_ulogic_vector; b: in integer) return std_ulogic_vector is
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variable res: std_ulogic_vector(0 to a'length-1);
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begin
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res := std_ulogic_vector(unsigned(a) + b);
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return res;
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end function;
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function dec(a: in std_ulogic_vector) return std_ulogic_vector is
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variable res: std_ulogic_vector(0 to a'length-1);
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begin
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res := std_ulogic_vector(unsigned(a) - 1);
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return res;
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end function;
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function eq(a: in std_ulogic_vector; b: in integer) return boolean is
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variable res: boolean;
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begin
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res := unsigned(a) = b;
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return res;
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end function;
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function eq(a: in std_ulogic_vector; b: in integer) return std_ulogic is
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variable res: std_ulogic;
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begin
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if unsigned(a) = b then
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res := '1';
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else
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res := '0';
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end if;
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return res;
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end function;
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function eq(a: in std_ulogic_vector; b: in std_ulogic_vector) return boolean is
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variable res: boolean;
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begin
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res := unsigned(a) = unsigned(b);
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return res;
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end function;
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function eq(a: in std_ulogic_vector; b: in std_ulogic_vector) return std_ulogic is
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variable res: std_ulogic;
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begin
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if unsigned(a) = unsigned(b) then
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res := '1';
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else
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res := '0';
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end if;
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return res;
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end function;
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function gate_and(a: in std_ulogic; b: in std_ulogic_vector) return std_ulogic_vector is
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variable res: std_ulogic_vector(0 to b'length-1);
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begin
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if a = '1' then
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res := b;
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else
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res := (others => '0');
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end if;
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return res;
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end function;
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function or_reduce(slv: in std_ulogic_vector) return std_ulogic is
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variable res: std_logic := '0';
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begin
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for i in 0 to slv'length-1 loop
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res := res or slv(i);
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end loop;
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return res;
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end function;
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function and_reduce(slv: in std_ulogic_vector) return std_ulogic is
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variable res: std_logic := '1';
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begin
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for i in 0 to slv'length-1 loop
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res := res and slv(i);
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end loop;
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return res;
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end function;
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function clog2(n : in integer) return integer is
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variable i : integer;
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variable j : integer := n - 1;
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variable res : integer := 1;
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begin
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for i in 0 to 31 loop
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if (j > 1) then
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j := j / 2;
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res := res + 1;
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else
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exit;
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end if;
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end loop;
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return res;
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end;
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function bus_ratio_enc(n : in integer) return std_ulogic_vector is
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variable res : std_ulogic_vector(3 downto 0);
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begin
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case n is
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when 1 => res := "0000";
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when 2 => res := "0001";
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when 4 => res := "0010";
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when 8 => res := "0011";
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when 16 => res := "0100";
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when 32 => res := "0101";
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when 64 => res := "0110";
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when 128 => res := "0111";
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when 256 => res := "1000";
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when 512 => res := "1001";
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when others => res := "1111";
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end case;
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return res;
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end;
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function bus_width_enc(n : in integer) return std_ulogic_vector is
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variable res : std_ulogic_vector(2 downto 0);
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begin
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case n is
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when 1 => res := "000";
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when 2 => res := "001";
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when 4 => res := "010";
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when 8 => res := "011";
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when 16 => res := "100";
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when others => res := "111";
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end case;
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return res;
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end;
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end package body mc_pkg;
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