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85 lines
2.0 KiB
VHDL
85 lines
2.0 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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library work;
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use work.utils.all;
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use work.wishbone_types.all;
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--! @brief Simple memory module for use in Wishbone-based systems.
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entity wishbone_bram_wrapper is
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generic(
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MEMORY_SIZE : natural := 4096; --! Memory size in bytes.
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RAM_INIT_FILE : string
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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-- Wishbone interface:
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wishbone_in : in wishbone_master_out;
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wishbone_out : out wishbone_slave_out
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);
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end entity wishbone_bram_wrapper;
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architecture behaviour of wishbone_bram_wrapper is
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constant ram_addr_bits : integer := log2ceil(MEMORY_SIZE) - 3;
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-- RAM interface
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signal ram_addr : std_logic_vector(ram_addr_bits - 1 downto 0);
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signal ram_we : std_ulogic;
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signal ram_re : std_ulogic;
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-- Others
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signal ack, ack_buf : std_ulogic;
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begin
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-- Actual RAM template
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ram_0: entity work.main_bram
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generic map(
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WIDTH => 64,
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HEIGHT_BITS => ram_addr_bits,
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MEMORY_SIZE => MEMORY_SIZE,
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RAM_INIT_FILE => RAM_INIT_FILE
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)
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port map(
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clk => clk,
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addr => ram_addr,
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din => wishbone_in.dat,
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dout => wishbone_out.dat,
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sel => wishbone_in.sel,
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re => ram_re,
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we => ram_we
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);
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-- Wishbone interface
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ram_addr <= wishbone_in.adr(ram_addr_bits - 1 downto 0);
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ram_we <= wishbone_in.stb and wishbone_in.cyc and wishbone_in.we;
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ram_re <= wishbone_in.stb and wishbone_in.cyc and not wishbone_in.we;
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wishbone_out.stall <= '0';
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wishbone_out.ack <= ack_buf;
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wb_0: process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' or wishbone_in.cyc = '0' then
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ack_buf <= '0';
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ack <= '0';
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else
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-- On loads, we have a delay cycle due to BRAM bufferring
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-- but not on stores. So try to send an early ack on a
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-- store if we aren't behind an existing load ack.
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--
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if ram_we = '1' and ack = '0' then
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ack_buf <= '1';
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else
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ack <= wishbone_in.stb;
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ack_buf <= ack;
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end if;
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end if;
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end if;
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end process;
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end architecture behaviour;
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