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Benjamin Herrenschmidt 573b6b4bc4 soc: Rework interconnect ... This changes the SoC interconnect such that the main 64-bit wishbone out of the processor is first split between only 3 slaves (BRAM, DRAM and a general "IO" bus) instead of all the slaves in the SoC. The IO bus leg is then latched and down-converted to 32 bits data width, before going through a second address decoder for the various IO devices. This significantly reduces routing and timing pressure on the main bus, allowing to get rid of frequent timing violations when synthetizing on small'ish FPGAs such as the Artix-7 35T found on the original Arty board. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		4 years ago
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include	litedram: Update to new LiteX/LiteDRAM version	4 years ago
libc	litedram: Add support for Microwatt-initialized controller	4 years ago
Makefile	sw: Add full memory map to .h and use it for litedram .lds	4 years ago
bin2hex.py	litedram: Add basic support for LiteX LiteDRAM	4 years ago
head.S	soc: Rework interconnect	4 years ago
main.c	litedram: Remove init delays	4 years ago
sdram_init.lds.S	soc: Rework interconnect	4 years ago