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microwatt/litedram/gen-src
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Benjamin Herrenschmidt 599fad117b litedram: Remove old "VexRiscV" based initializations 
Support for this has bitrotted and would require refactoring of L2 to
be brought back. It's also not really needed anymore now that we ship
pre-generated litedram and that LiteX supports what we do.

So take it out, which simplifies some of the scripts as well. This also
fixes up CSR alignment the sim model.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 		4 years ago
..
sdram_init litedram: Add an L2 cache with store queue 4 years ago
arty.yml litedram: Remove old "VexRiscV" based initializations 4 years ago
dram-init-mem.vhdl litedram: Add support for booting without BRAM 4 years ago
generate.py litedram: Remove old "VexRiscV" based initializations 4 years ago
nexys-video.yml litedram: Remove old "VexRiscV" based initializations 4 years ago
no-init-mem.vhdl litedram: Split the init memory from the main wrapper 4 years ago
sim.yml litedram: Remove old "VexRiscV" based initializations 4 years ago