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caravel-mpw7-20221125
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branch-alias
trace-test
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litedram-update
liteeth-update
fix-sdcard
fpu-init
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unused-sig
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fpu-typo
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caravel-mpw6-20220530
caravel-mpw5-20220323
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alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
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microwatt/litedram/generated
History
Benjamin Herrenschmidt f9f18906a3 soc: Rename wb_dram_ctrl to wb_ext_io and rework decoding 
This makes the control bus currently going out of "soc" towards
litedram more generic for external IO devices added by the
top-level rather than inside the SoC proper.

This is mostly renaming of signals and a small change on how the
address decoder operates, using a separate "cascaded" decode for
the external IOs.

We make the region 0xc8nn_nnnn be the "external IO" region for
now.

This will make it easier / cleaner to add more external devices.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 		5 years ago
..
arty soc: Rename wb_dram_ctrl to wb_ext_io and rework decoding 5 years ago
nexys-video soc: Rename wb_dram_ctrl to wb_ext_io and rework decoding 5 years ago
sim soc: Rename wb_dram_ctrl to wb_ext_io and rework decoding 5 years ago