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94 lines
2.5 KiB
VHDL
94 lines
2.5 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.helpers.all;
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-- 2 cycle LSU
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-- We calculate the address in the first cycle
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entity loadstore1 is
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port (
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clk : in std_ulogic;
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l_in : in Execute1ToLoadstore1Type;
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l_out : out Loadstore1ToDcacheType
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);
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end loadstore1;
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architecture behave of loadstore1 is
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signal r, rin : Loadstore1ToDcacheType;
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signal lsu_sum : std_ulogic_vector(63 downto 0);
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begin
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-- Calculate the address in the first cycle
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lsu_sum <= std_ulogic_vector(unsigned(l_in.addr1) + unsigned(l_in.addr2)) when l_in.valid = '1' else (others => '0');
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loadstore1_0: process(clk)
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begin
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if rising_edge(clk) then
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r <= rin;
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end if;
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end process;
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loadstore1_1: process(all)
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variable v : Loadstore1ToDcacheType;
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variable brev_lenm1 : unsigned(2 downto 0);
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variable byte_offset : unsigned(2 downto 0);
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variable j : integer;
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variable k : unsigned(2 downto 0);
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begin
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v := r;
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v.valid := l_in.valid;
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v.load := l_in.load;
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v.write_reg := l_in.write_reg;
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v.length := l_in.length;
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v.byte_reverse := l_in.byte_reverse;
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v.sign_extend := l_in.sign_extend;
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v.update := l_in.update;
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v.update_reg := l_in.update_reg;
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v.xerc := l_in.xerc;
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v.reserve := l_in.reserve;
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v.rc := l_in.rc;
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-- XXX Temporary hack. Mark the op as non-cachable if the address
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-- is the form 0xc-------
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--
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-- This will have to be replaced by a combination of implementing the
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-- proper HV CI load/store instructions and having an MMU to get the I
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-- bit otherwise.
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if lsu_sum(31 downto 28) = "1100" then
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v.nc := '1';
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else
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v.nc := '0';
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end if;
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-- XXX Do length_to_sel here ?
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-- Do byte reversing and rotating for stores in the first cycle
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if v.load = '0' then
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byte_offset := unsigned(lsu_sum(2 downto 0));
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brev_lenm1 := "000";
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if l_in.byte_reverse = '1' then
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brev_lenm1 := unsigned(l_in.length(2 downto 0)) - 1;
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end if;
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for i in 0 to 7 loop
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k := (to_unsigned(i, 3) xor brev_lenm1) + byte_offset;
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j := to_integer(k) * 8;
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v.data(j + 7 downto j) := l_in.data(i * 8 + 7 downto i * 8);
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end loop;
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end if;
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v.addr := lsu_sum;
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-- Update registers
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rin <= v;
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-- Update outputs
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l_out <= r;
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end process;
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end;
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