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482 lines
17 KiB
VHDL
482 lines
17 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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-- Radix MMU
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-- Supports 4-level trees as in arch 3.0B, but not the two-step translation for
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-- guests under a hypervisor (i.e. there is no gRA -> hRA translation).
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entity mmu is
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port (
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clk : in std_ulogic;
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rst : in std_ulogic;
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l_in : in Loadstore1ToMmuType;
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l_out : out MmuToLoadstore1Type;
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d_out : out MmuToDcacheType;
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d_in : in DcacheToMmuType;
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i_out : out MmuToIcacheType
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);
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end mmu;
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architecture behave of mmu is
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type state_t is (IDLE,
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DO_TLBIE,
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TLB_WAIT,
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PROC_TBL_READ,
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PROC_TBL_WAIT,
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SEGMENT_CHECK,
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RADIX_LOOKUP,
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RADIX_READ_WAIT,
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RADIX_LOAD_TLB,
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RADIX_FINISH
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);
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type reg_stage_t is record
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-- latched request from loadstore1
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valid : std_ulogic;
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iside : std_ulogic;
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store : std_ulogic;
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priv : std_ulogic;
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addr : std_ulogic_vector(63 downto 0);
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inval_all : std_ulogic;
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-- config SPRs
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prtbl : std_ulogic_vector(63 downto 0);
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pid : std_ulogic_vector(31 downto 0);
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-- internal state
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state : state_t;
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done : std_ulogic;
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err : std_ulogic;
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pgtbl0 : std_ulogic_vector(63 downto 0);
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pt0_valid : std_ulogic;
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pgtbl3 : std_ulogic_vector(63 downto 0);
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pt3_valid : std_ulogic;
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shift : unsigned(5 downto 0);
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mask_size : unsigned(4 downto 0);
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pgbase : std_ulogic_vector(55 downto 0);
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pde : std_ulogic_vector(63 downto 0);
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invalid : std_ulogic;
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badtree : std_ulogic;
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segerror : std_ulogic;
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perm_err : std_ulogic;
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rc_error : std_ulogic;
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end record;
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signal r, rin : reg_stage_t;
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signal addrsh : std_ulogic_vector(15 downto 0);
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signal mask : std_ulogic_vector(15 downto 0);
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signal finalmask : std_ulogic_vector(43 downto 0);
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begin
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-- Multiplex internal SPR values back to loadstore1, selected
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-- by l_in.sprn.
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l_out.sprval <= r.prtbl when l_in.sprn(9) = '1' else x"00000000" & r.pid;
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mmu_0: process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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r.state <= IDLE;
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r.valid <= '0';
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r.pt0_valid <= '0';
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r.pt3_valid <= '0';
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r.prtbl <= (others => '0');
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else
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if rin.valid = '1' then
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report "MMU got tlb miss for " & to_hstring(rin.addr);
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end if;
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if l_out.done = '1' then
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report "MMU completing op without error";
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end if;
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if l_out.err = '1' then
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report "MMU completing op with err invalid=" & std_ulogic'image(l_out.invalid) &
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" badtree=" & std_ulogic'image(l_out.badtree);
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end if;
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if rin.state = RADIX_LOOKUP then
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report "radix lookup shift=" & integer'image(to_integer(rin.shift)) &
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" msize=" & integer'image(to_integer(rin.mask_size));
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end if;
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if r.state = RADIX_LOOKUP then
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report "send load addr=" & to_hstring(d_out.addr) &
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" addrsh=" & to_hstring(addrsh) & " mask=" & to_hstring(mask);
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end if;
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r <= rin;
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end if;
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end if;
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end process;
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-- Shift address bits 61--12 right by 0--47 bits and
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-- supply the least significant 16 bits of the result.
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addrshifter: process(all)
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variable sh1 : std_ulogic_vector(30 downto 0);
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variable sh2 : std_ulogic_vector(18 downto 0);
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variable result : std_ulogic_vector(15 downto 0);
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begin
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case r.shift(5 downto 4) is
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when "00" =>
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sh1 := r.addr(42 downto 12);
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when "01" =>
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sh1 := r.addr(58 downto 28);
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when others =>
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sh1 := "0000000000000" & r.addr(61 downto 44);
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end case;
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case r.shift(3 downto 2) is
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when "00" =>
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sh2 := sh1(18 downto 0);
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when "01" =>
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sh2 := sh1(22 downto 4);
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when "10" =>
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sh2 := sh1(26 downto 8);
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when others =>
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sh2 := sh1(30 downto 12);
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end case;
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case r.shift(1 downto 0) is
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when "00" =>
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result := sh2(15 downto 0);
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when "01" =>
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result := sh2(16 downto 1);
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when "10" =>
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result := sh2(17 downto 2);
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when others =>
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result := sh2(18 downto 3);
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end case;
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addrsh <= result;
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end process;
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-- generate mask for extracting address fields for PTE address generation
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addrmaskgen: process(all)
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variable m : std_ulogic_vector(15 downto 0);
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begin
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-- mask_count has to be >= 5
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m := x"001f";
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for i in 5 to 15 loop
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if i < to_integer(r.mask_size) then
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m(i) := '1';
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end if;
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end loop;
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mask <= m;
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end process;
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-- generate mask for extracting address bits to go in TLB entry
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-- in order to support pages > 4kB
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finalmaskgen: process(all)
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variable m : std_ulogic_vector(43 downto 0);
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begin
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m := (others => '0');
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for i in 0 to 43 loop
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if i < to_integer(r.shift) then
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m(i) := '1';
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end if;
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end loop;
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finalmask <= m;
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end process;
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mmu_1: process(all)
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variable v : reg_stage_t;
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variable dcreq : std_ulogic;
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variable tlb_load : std_ulogic;
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variable itlb_load : std_ulogic;
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variable tlbie_req : std_ulogic;
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variable prtbl_rd : std_ulogic;
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variable pt_valid : std_ulogic;
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variable effpid : std_ulogic_vector(31 downto 0);
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variable prtable_addr : std_ulogic_vector(63 downto 0);
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variable rts : unsigned(5 downto 0);
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variable mbits : unsigned(5 downto 0);
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variable pgtable_addr : std_ulogic_vector(63 downto 0);
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variable pte : std_ulogic_vector(63 downto 0);
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variable tlb_data : std_ulogic_vector(63 downto 0);
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variable nonzero : std_ulogic;
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variable pgtbl : std_ulogic_vector(63 downto 0);
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variable perm_ok : std_ulogic;
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variable rc_ok : std_ulogic;
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variable addr : std_ulogic_vector(63 downto 0);
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variable data : std_ulogic_vector(63 downto 0);
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begin
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v := r;
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v.valid := '0';
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dcreq := '0';
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v.done := '0';
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v.err := '0';
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v.invalid := '0';
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v.badtree := '0';
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v.segerror := '0';
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v.perm_err := '0';
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v.rc_error := '0';
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tlb_load := '0';
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itlb_load := '0';
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tlbie_req := '0';
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v.inval_all := '0';
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prtbl_rd := '0';
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-- Radix tree data structures in memory are big-endian,
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-- so we need to byte-swap them
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for i in 0 to 7 loop
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data(i * 8 + 7 downto i * 8) := d_in.data((7 - i) * 8 + 7 downto (7 - i) * 8);
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end loop;
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case r.state is
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when IDLE =>
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if l_in.addr(63) = '0' then
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pgtbl := r.pgtbl0;
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pt_valid := r.pt0_valid;
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else
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pgtbl := r.pgtbl3;
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pt_valid := r.pt3_valid;
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end if;
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-- rts == radix tree size, # address bits being translated
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rts := unsigned('0' & pgtbl(62 downto 61) & pgtbl(7 downto 5));
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-- mbits == # address bits to index top level of tree
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mbits := unsigned('0' & pgtbl(4 downto 0));
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-- set v.shift to rts so that we can use finalmask for the segment check
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v.shift := rts;
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v.mask_size := mbits(4 downto 0);
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v.pgbase := pgtbl(55 downto 8) & x"00";
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if l_in.valid = '1' then
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v.addr := l_in.addr;
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v.iside := l_in.iside;
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v.store := not (l_in.load or l_in.iside);
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v.priv := l_in.priv;
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if l_in.tlbie = '1' then
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-- Invalidate all iTLB/dTLB entries for tlbie with
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-- RB[IS] != 0 or RB[AP] != 0, or for slbia
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v.inval_all := l_in.slbia or l_in.addr(11) or l_in.addr(10) or
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l_in.addr(7) or l_in.addr(6) or l_in.addr(5);
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-- The RIC field of the tlbie instruction comes across on the
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-- sprn bus as bits 2--3. RIC=2 flushes process table caches.
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if l_in.sprn(3) = '1' then
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v.pt0_valid := '0';
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v.pt3_valid := '0';
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end if;
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v.state := DO_TLBIE;
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else
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v.valid := '1';
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if pt_valid = '0' then
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-- need to fetch process table entry
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-- set v.shift so we can use finalmask for generating
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-- the process table entry address
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v.shift := unsigned('0' & r.prtbl(4 downto 0));
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v.state := PROC_TBL_READ;
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elsif mbits = 0 then
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-- Use RPDS = 0 to disable radix tree walks
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v.state := RADIX_FINISH;
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v.invalid := '1';
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else
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v.state := SEGMENT_CHECK;
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end if;
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end if;
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end if;
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if l_in.mtspr = '1' then
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-- Move to PID needs to invalidate L1 TLBs and cached
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-- pgtbl0 value. Move to PRTBL does that plus
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-- invalidating the cached pgtbl3 value as well.
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if l_in.sprn(9) = '0' then
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v.pid := l_in.rs(31 downto 0);
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else
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v.prtbl := l_in.rs;
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v.pt3_valid := '0';
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end if;
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v.pt0_valid := '0';
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v.inval_all := '1';
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v.state := DO_TLBIE;
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end if;
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when DO_TLBIE =>
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dcreq := '1';
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tlbie_req := '1';
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v.state := TLB_WAIT;
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when TLB_WAIT =>
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if d_in.done = '1' then
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v.state := RADIX_FINISH;
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end if;
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when PROC_TBL_READ =>
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dcreq := '1';
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prtbl_rd := '1';
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v.state := PROC_TBL_WAIT;
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when PROC_TBL_WAIT =>
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if d_in.done = '1' then
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if r.addr(63) = '1' then
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v.pgtbl3 := data;
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v.pt3_valid := '1';
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else
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v.pgtbl0 := data;
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v.pt0_valid := '1';
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end if;
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-- rts == radix tree size, # address bits being translated
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rts := unsigned('0' & data(62 downto 61) & data(7 downto 5));
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-- mbits == # address bits to index top level of tree
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mbits := unsigned('0' & data(4 downto 0));
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-- set v.shift to rts so that we can use finalmask for the segment check
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v.shift := rts;
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v.mask_size := mbits(4 downto 0);
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v.pgbase := data(55 downto 8) & x"00";
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if mbits = 0 then
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v.state := RADIX_FINISH;
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v.invalid := '1';
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else
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v.state := SEGMENT_CHECK;
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end if;
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end if;
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if d_in.err = '1' then
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v.state := RADIX_FINISH;
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v.badtree := '1';
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end if;
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when SEGMENT_CHECK =>
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mbits := '0' & r.mask_size;
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v.shift := r.shift + (31 - 12) - mbits;
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nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
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if r.addr(63) /= r.addr(62) or nonzero = '1' then
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v.state := RADIX_FINISH;
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v.segerror := '1';
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elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
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v.state := RADIX_FINISH;
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v.badtree := '1';
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else
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v.state := RADIX_LOOKUP;
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end if;
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when RADIX_LOOKUP =>
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dcreq := '1';
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v.state := RADIX_READ_WAIT;
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when RADIX_READ_WAIT =>
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if d_in.done = '1' then
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v.pde := data;
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-- test valid bit
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if data(63) = '1' then
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-- test leaf bit
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if data(62) = '1' then
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-- check permissions and RC bits
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perm_ok := '0';
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if r.priv = '1' or data(3) = '0' then
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if r.iside = '0' then
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perm_ok := data(1) or (data(2) and not r.store);
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else
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-- no IAMR, so no KUEP support for now
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-- deny execute permission if cache inhibited
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perm_ok := data(0) and not data(5);
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end if;
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end if;
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rc_ok := data(8) and (data(7) or not r.store);
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if perm_ok = '1' and rc_ok = '1' then
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v.state := RADIX_LOAD_TLB;
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else
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v.state := RADIX_FINISH;
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v.perm_err := not perm_ok;
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-- permission error takes precedence over RC error
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v.rc_error := perm_ok;
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end if;
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else
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mbits := unsigned('0' & data(4 downto 0));
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if mbits < 5 or mbits > 16 or mbits > r.shift then
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v.state := RADIX_FINISH;
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v.badtree := '1';
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else
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v.shift := v.shift - mbits;
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v.mask_size := mbits(4 downto 0);
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v.pgbase := data(55 downto 8) & x"00";
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v.state := RADIX_LOOKUP;
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end if;
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end if;
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else
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-- non-present PTE, generate a DSI
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v.state := RADIX_FINISH;
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v.invalid := '1';
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end if;
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end if;
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if d_in.err = '1' then
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v.state := RADIX_FINISH;
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v.badtree := '1';
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end if;
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when RADIX_LOAD_TLB =>
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tlb_load := '1';
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if r.iside = '0' then
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dcreq := '1';
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v.state := TLB_WAIT;
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else
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itlb_load := '1';
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v.state := IDLE;
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end if;
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when RADIX_FINISH =>
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v.state := IDLE;
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end case;
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if v.state = RADIX_FINISH or (v.state = RADIX_LOAD_TLB and r.iside = '1') then
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v.err := v.invalid or v.badtree or v.segerror or v.perm_err or v.rc_error;
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v.done := not v.err;
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end if;
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if r.addr(63) = '1' then
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effpid := x"00000000";
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else
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effpid := r.pid;
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end if;
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prtable_addr := x"00" & r.prtbl(55 downto 36) &
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((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
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(effpid(31 downto 8) and finalmask(23 downto 0))) &
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effpid(7 downto 0) & "0000";
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pgtable_addr := x"00" & r.pgbase(55 downto 19) &
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((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
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"000";
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pte := x"00" &
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((r.pde(55 downto 12) and not finalmask) or (r.addr(55 downto 12) and finalmask))
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& r.pde(11 downto 0);
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-- update registers
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rin <= v;
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-- drive outputs
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if tlbie_req = '1' then
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addr := r.addr;
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tlb_data := (others => '0');
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elsif tlb_load = '1' then
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addr := r.addr(63 downto 12) & x"000";
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tlb_data := pte;
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elsif prtbl_rd = '1' then
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addr := prtable_addr;
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tlb_data := (others => '0');
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else
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addr := pgtable_addr;
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tlb_data := (others => '0');
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end if;
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l_out.done <= r.done;
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l_out.err <= r.err;
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l_out.invalid <= r.invalid;
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l_out.badtree <= r.badtree;
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l_out.segerr <= r.segerror;
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l_out.perm_error <= r.perm_err;
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l_out.rc_error <= r.rc_error;
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d_out.valid <= dcreq;
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d_out.tlbie <= tlbie_req;
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d_out.doall <= r.inval_all;
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d_out.tlbld <= tlb_load;
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d_out.addr <= addr;
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d_out.pte <= tlb_data;
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i_out.tlbld <= itlb_load;
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i_out.tlbie <= tlbie_req;
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i_out.doall <= r.inval_all;
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i_out.addr <= addr;
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i_out.pte <= tlb_data;
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end process;
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end;
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