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microwatt
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microwatt/fpga
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Benjamin Herrenschmidt a93d9e77c9 litedram: Remove remnants of riscv-inits 
We still had some wires bringing an extra serial port out of
litedram for the built-in riscv processor. This is all gone now
so take them out.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
..
LICENSE Initial import of microwatt
arty_a7.xdc fpga: Hookup Arty to litedram
clk_gen_bypass.vhd Fix clk_gen_bypass
clk_gen_mcmm.vhd Improve PLL/MMCM clocks configuration
clk_gen_plle2.vhd Improve PLL/MMCM clocks configuration
cmod_a7-35.xdc Add SPI configuration to Xilinx constraint files
firmware.hex Add a few more FPGA related files
hello_world.hex hello_world: Use new headers and frequency from syscon
main_bram.vhdl Fix some ghdlsynth issues with fpga_bram
nexys-video.xdc fpga: Hookup nexys-video to litedram
nexys_a7.xdc Add SPI configuration to Xilinx constraint files
pp_fifo.vhd pp_fifo: Fix full fifo losing all data on simultaneous push & pop
pp_soc_uart.vhd pp_soc_uart: Fix rx synchronizers and ensure stable tx init state
pp_utilities.vhd Initial import of microwatt
soc_reset.vhdl soc_reset: Use counters, add synchronizers
soc_reset_tb.vhdl Exit cleanly from testbench on success
top-arty.vhdl litedram: Remove remnants of riscv-inits
top-generic.vhdl soc: Rework interconnect
top-nexys-video.vhdl litedram: Remove remnants of riscv-inits