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79 lines
1.4 KiB
VHDL
79 lines
1.4 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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entity fetch1 is
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generic(
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RESET_ADDRESS : std_logic_vector(63 downto 0)
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);
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port(
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clk : in std_ulogic;
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rst : in std_ulogic;
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-- Control inputs:
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fetch_one_in : in std_ulogic;
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-- redirect from execution unit
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e_in : in Execute1ToFetch1Type;
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-- fetch data out
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f_out : out Fetch1ToFetch2Type
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);
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end entity fetch1;
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architecture behaviour of fetch1 is
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type reg_type is record
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pc : std_ulogic_vector(63 downto 0);
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fetch_one : std_ulogic;
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end record;
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signal r : reg_type;
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signal rin : reg_type;
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begin
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regs : process(clk)
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begin
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if rising_edge(clk) then
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r <= rin;
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end if;
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end process;
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comb : process(all)
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variable v : reg_type;
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variable fetch_valid : std_ulogic;
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variable fetch_nia : std_ulogic_vector(63 downto 0);
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begin
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v := r;
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fetch_valid := '0';
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fetch_nia := (others => '0');
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v.fetch_one := v.fetch_one or fetch_one_in;
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if e_in.redirect = '1' then
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v.pc := e_in.redirect_nia;
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end if;
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if v.fetch_one = '1' then
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fetch_nia := v.pc;
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fetch_valid := '1';
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v.pc := std_logic_vector(unsigned(v.pc) + 4);
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v.fetch_one := '0';
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end if;
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if rst = '1' then
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v.pc := RESET_ADDRESS;
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v.fetch_one := '0';
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end if;
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rin <= v;
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f_out.valid <= fetch_valid;
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f_out.nia <= fetch_nia;
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end process;
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end architecture behaviour;
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