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Benjamin Herrenschmidt a3857aac94 litedram: Add an L2 cache with store queue ... This adds a cache between the wishbone and litedram with the following features (at this point, it's still evolving) - 128 bytes line width in order to have a reasonable amount of litedram pipelining on the 128-bit wide data port. - Configurable geometry otherwise - Stores are acked immediately on wishbone whether hit or miss (minus a 2 cycles delay if there's a previous load response in the way) and sent to LiteDRAM via 8 entries (configurable) store queue Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		5 years ago
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include	litedram: Add an L2 cache with store queue	5 years ago
libc	litedram: Add support for Microwatt-initialized controller	5 years ago
Makefile	litedram: Add simulation support	5 years ago
bin2hex.py	litedram: Add basic support for LiteX LiteDRAM	5 years ago
head.S	soc: Rework interconnect	5 years ago
main.c	litedram: Add support for booting without BRAM	5 years ago
sdram_init.lds.S	soc: Rework interconnect	5 years ago