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caravel-mpw7-20221125
caravel-mpw7-20220822
branch-alias
trace-test
gitignore
litedram-update
liteeth-update
fix-sdcard
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
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microwatt/litedram/gen-src
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Paul Mackerras 82dacf2c1c ECPIX-5: Wire up SPI flash 
The flash chip on my board is an ISSI IS26LP256P chip.  The ISSI chip
requires slightly different setup for quad mode from the other brands,
but works fine with the existing SPI flash interface logic here.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 		2 months ago
..
sdram_init ECPIX-5: Wire up SPI flash 2 months ago
acorn-cle-215.yml litedram: disable block_until_ready, regenerate 2 years ago
arty.yml litedram: disable block_until_ready, regenerate 2 years ago
dram-init-mem.vhdl Make wishbone addresses be in units of doublewords or words 3 years ago
generate.py litedram: Add orangecrab-85-0.2 target 2 years ago
genesys2.yml litedram: disable block_until_ready, regenerate 2 years ago
nexys-video.yml litedram: disable block_until_ready, regenerate 2 years ago
no-init-mem.vhdl litedram: Split the init memory from the main wrapper 4 years ago
orangecrab-85-0.2.yml litedram: Add orangecrab-85-0.2 target 2 years ago
sim.yml litedram: disable block_until_ready, regenerate 2 years ago
wukong-v2.yml litedram: disable block_until_ready, regenerate 2 years ago