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67 lines
1.3 KiB
VHDL
67 lines
1.3 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.wishbone_types.all;
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entity fetch2 is
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port(
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clk : in std_ulogic;
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rst : in std_ulogic;
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stall_in : in std_ulogic;
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stall_out : out std_ulogic;
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flush_in : in std_ulogic;
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stop_in : in std_ulogic;
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i_in : in IcacheToFetch2Type;
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i_out : out Fetch2ToIcacheType;
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f_in : in Fetch1ToFetch2Type;
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f_out : out Fetch2ToDecode1Type
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);
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end entity fetch2;
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architecture behaviour of fetch2 is
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signal r, rin : Fetch2ToDecode1Type;
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begin
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regs : process(clk)
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begin
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if rising_edge(clk) then
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-- Output state remains unchanged on stall, unless we are flushing
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if rst = '1' or flush_in = '1' or stall_in = '0' then
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r <= rin;
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end if;
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end if;
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end process;
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comb : process(all)
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variable v : Fetch2ToDecode1Type;
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begin
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v := r;
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-- asynchronous icache lookup
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i_out.req <= '1';
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i_out.addr <= f_in.nia;
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v.valid := i_in.ack;
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v.nia := f_in.nia;
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v.insn := i_in.insn;
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stall_out <= stop_in or not i_in.ack;
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if flush_in = '1' or stop_in = '1' then
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v.valid := '0';
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end if;
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v.stop_mark := stop_in;
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-- Update registers
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rin <= v;
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-- Update outputs
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f_out <= r;
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end process;
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end architecture behaviour;
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