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Anton Blanchard f5424f8e71 Reduce simulated and default FPGA RAM to 384kB ... Micropython has been able to fit into 384kB for ages, so lets reduce our simulated RAM. This is useful for testing if micropython will run on an ECP5 85k, which has enough BRAM for 384kB but not enough for 512kB. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>		5 years ago
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LICENSE	Initial import of microwatt	5 years ago
arty_a7.xdc	Add SPI configuration to Xilinx constraint files	5 years ago
clk_gen_bypass.vhd	Fix clk_gen_bypass	5 years ago
clk_gen_mcmm.vhd	Improve PLL/MMCM clocks configuration	5 years ago
clk_gen_plle2.vhd	Improve PLL/MMCM clocks configuration	5 years ago
cmod_a7-35.xdc	Add SPI configuration to Xilinx constraint files	5 years ago
firmware.hex	Add a few more FPGA related files	5 years ago
hello_world.hex	Rebuild hello world assuming a 50MHz clock	5 years ago
main_bram.vhdl	Fix some ghdlsynth issues with fpga_bram	5 years ago
nexys-video.xdc	Add SPI configuration to Xilinx constraint files	5 years ago
nexys_a7.xdc	Add SPI configuration to Xilinx constraint files	5 years ago
pp_fifo.vhd	fifo: Reformat	5 years ago
pp_soc_uart.vhd	pp_uart: reformat	5 years ago
pp_utilities.vhd	Initial import of microwatt	5 years ago
soc_reset.vhdl	Rework SOC reset	5 years ago
soc_reset_tb.vhdl	Rework SOC reset	5 years ago
toplevel.vhdl	Reduce simulated and default FPGA RAM to 384kB	5 years ago