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444 lines
18 KiB
VHDL
444 lines
18 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.utils.all;
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use work.common.all;
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use work.wishbone_types.all;
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entity core_debug is
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generic (
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-- Length of log buffer
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LOG_LENGTH : natural := 512
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);
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port (
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clk : in std_logic;
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rst : in std_logic;
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dmi_addr : in std_ulogic_vector(3 downto 0);
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dmi_din : in std_ulogic_vector(63 downto 0);
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dmi_dout : out std_ulogic_vector(63 downto 0);
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dmi_req : in std_ulogic;
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dmi_wr : in std_ulogic;
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dmi_ack : out std_ulogic;
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-- Debug actions
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core_stop : out std_ulogic;
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core_rst : out std_ulogic;
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icache_rst : out std_ulogic;
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-- Core status inputs
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terminate : in std_ulogic;
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core_stopped : in std_ulogic;
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nia : in std_ulogic_vector(63 downto 0);
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msr : in std_ulogic_vector(63 downto 0);
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wb_snoop_in : in wishbone_master_out := wishbone_master_out_init;
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-- GPR/FPR register read port
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dbg_gpr_req : out std_ulogic;
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dbg_gpr_ack : in std_ulogic;
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dbg_gpr_addr : out gspr_index_t;
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dbg_gpr_data : in std_ulogic_vector(63 downto 0);
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-- SPR register read port for SPRs in execute1
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dbg_spr_req : out std_ulogic;
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dbg_spr_ack : in std_ulogic;
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dbg_spr_addr : out std_ulogic_vector(7 downto 0);
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dbg_spr_data : in std_ulogic_vector(63 downto 0);
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-- SPR register read port for SPRs in loadstore1 and mmu
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dbg_ls_spr_req : out std_ulogic;
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dbg_ls_spr_ack : in std_ulogic;
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dbg_ls_spr_addr : out std_ulogic_vector(1 downto 0);
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dbg_ls_spr_data : in std_ulogic_vector(63 downto 0);
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-- Core logging data
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log_data : in std_ulogic_vector(255 downto 0);
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log_read_addr : in std_ulogic_vector(31 downto 0);
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log_read_data : out std_ulogic_vector(63 downto 0);
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log_write_addr : out std_ulogic_vector(31 downto 0);
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-- Misc
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terminated_out : out std_ulogic
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);
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end core_debug;
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architecture behave of core_debug is
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-- DMI needs fixing... make a one clock pulse
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signal dmi_req_1: std_ulogic;
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-- CTRL register (direct actions, write 1 to act, read back 0)
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-- bit 0 : Core stop
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-- bit 1 : Core reset (doesn't clear stop)
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-- bit 2 : Icache reset
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-- bit 3 : Single step
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-- bit 4 : Core start
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constant DBG_CORE_CTRL : std_ulogic_vector(3 downto 0) := "0000";
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constant DBG_CORE_CTRL_STOP : integer := 0;
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constant DBG_CORE_CTRL_RESET : integer := 1;
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constant DBG_CORE_CTRL_ICRESET : integer := 2;
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constant DBG_CORE_CTRL_STEP : integer := 3;
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constant DBG_CORE_CTRL_START : integer := 4;
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-- STAT register (read only)
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-- bit 0 : Core stopping (wait til bit 1 set)
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-- bit 1 : Core stopped
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-- bit 2 : Core terminated (clears with start or reset)
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constant DBG_CORE_STAT : std_ulogic_vector(3 downto 0) := "0001";
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constant DBG_CORE_STAT_STOPPING : integer := 0;
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constant DBG_CORE_STAT_STOPPED : integer := 1;
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constant DBG_CORE_STAT_TERM : integer := 2;
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-- NIA register (read only for now)
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constant DBG_CORE_NIA : std_ulogic_vector(3 downto 0) := "0010";
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-- MSR (read only)
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constant DBG_CORE_MSR : std_ulogic_vector(3 downto 0) := "0011";
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-- GSPR register index
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constant DBG_CORE_GSPR_INDEX : std_ulogic_vector(3 downto 0) := "0100";
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-- GSPR register data
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constant DBG_CORE_GSPR_DATA : std_ulogic_vector(3 downto 0) := "0101";
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-- Log buffer address and data registers
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constant DBG_CORE_LOG_ADDR : std_ulogic_vector(3 downto 0) := "0110";
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constant DBG_CORE_LOG_DATA : std_ulogic_vector(3 downto 0) := "0111";
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constant DBG_CORE_LOG_TRIGGER : std_ulogic_vector(3 downto 0) := "1000";
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constant DBG_CORE_LOG_MTRIGGER : std_ulogic_vector(3 downto 0) := "1001";
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constant LOG_INDEX_BITS : natural := log2(LOG_LENGTH);
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-- Some internal wires
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signal stat_reg : std_ulogic_vector(63 downto 0);
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-- Some internal latches
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signal stopping : std_ulogic;
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signal do_step : std_ulogic;
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signal do_reset : std_ulogic;
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signal do_icreset : std_ulogic;
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signal terminated : std_ulogic;
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signal do_gspr_rd : std_ulogic;
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signal gspr_index : std_ulogic_vector(7 downto 0);
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signal gspr_data : std_ulogic_vector(63 downto 0);
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signal spr_index_valid : std_ulogic;
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signal log_dmi_addr : std_ulogic_vector(31 downto 0) := (others => '0');
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signal log_dmi_data : std_ulogic_vector(63 downto 0) := (others => '0');
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signal log_dmi_trigger : std_ulogic_vector(63 downto 0) := (others => '0');
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signal log_mem_trigger : std_ulogic_vector(63 downto 0) := (others => '0');
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signal do_log_trigger : std_ulogic := '0';
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signal do_log_mtrigger : std_ulogic := '0';
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signal trigger_was_log : std_ulogic := '0';
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signal trigger_was_mem : std_ulogic := '0';
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signal do_dmi_log_rd : std_ulogic;
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signal dmi_read_log_data : std_ulogic;
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signal dmi_read_log_data_1 : std_ulogic;
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signal log_trigger_delay : integer range 0 to 255 := 0;
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begin
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-- Single cycle register accesses on DMI except for GSPR data
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dmi_ack <= dmi_req when dmi_addr /= DBG_CORE_GSPR_DATA
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else dbg_gpr_ack or dbg_spr_ack or dbg_ls_spr_ack;
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-- Status register read composition
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stat_reg <= (2 => terminated,
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1 => core_stopped,
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0 => stopping,
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others => '0');
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gspr_data <= dbg_gpr_data when gspr_index(5) = '0' else
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dbg_ls_spr_data when dbg_ls_spr_req = '1' else
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dbg_spr_data when spr_index_valid = '1' else
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(others => '0');
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-- DMI read data mux
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with dmi_addr select dmi_dout <=
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stat_reg when DBG_CORE_STAT,
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nia when DBG_CORE_NIA,
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msr when DBG_CORE_MSR,
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gspr_data when DBG_CORE_GSPR_DATA,
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log_write_addr & log_dmi_addr when DBG_CORE_LOG_ADDR,
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log_dmi_data when DBG_CORE_LOG_DATA,
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log_dmi_trigger when DBG_CORE_LOG_TRIGGER,
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log_mem_trigger when DBG_CORE_LOG_MTRIGGER,
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(others => '0') when others;
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-- DMI writes
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reg_write: process(clk)
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begin
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if rising_edge(clk) then
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-- Reset the 1-cycle "do" signals
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do_step <= '0';
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do_reset <= '0';
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do_icreset <= '0';
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do_dmi_log_rd <= '0';
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if (rst) then
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stopping <= '0';
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terminated <= '0';
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log_trigger_delay <= 0;
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gspr_index <= (others => '0');
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log_dmi_addr <= (others => '0');
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trigger_was_log <= '0';
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trigger_was_mem <= '0';
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else
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if do_log_trigger = '1' or do_log_mtrigger = '1' or log_trigger_delay /= 0 then
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if log_trigger_delay = 255 or
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(LOG_LENGTH < 1024 and log_trigger_delay = LOG_LENGTH / 4) then
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log_dmi_trigger(1) <= trigger_was_log;
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log_mem_trigger(1) <= trigger_was_mem;
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log_trigger_delay <= 0;
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trigger_was_log <= '0';
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trigger_was_mem <= '0';
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else
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log_trigger_delay <= log_trigger_delay + 1;
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end if;
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end if;
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if do_log_trigger = '1' then
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trigger_was_log <= '1';
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end if;
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if do_log_mtrigger = '1' then
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trigger_was_mem <= '1';
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end if;
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-- Edge detect on dmi_req for 1-shot pulses
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dmi_req_1 <= dmi_req;
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if dmi_req = '1' and dmi_req_1 = '0' then
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if dmi_wr = '1' then
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report("DMI write to " & to_hstring(dmi_addr));
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-- Control register actions
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if dmi_addr = DBG_CORE_CTRL then
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if dmi_din(DBG_CORE_CTRL_RESET) = '1' then
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do_reset <= '1';
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terminated <= '0';
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end if;
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if dmi_din(DBG_CORE_CTRL_STOP) = '1' then
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stopping <= '1';
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end if;
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if dmi_din(DBG_CORE_CTRL_STEP) = '1' then
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do_step <= '1';
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terminated <= '0';
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end if;
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if dmi_din(DBG_CORE_CTRL_ICRESET) = '1' then
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do_icreset <= '1';
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end if;
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if dmi_din(DBG_CORE_CTRL_START) = '1' then
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stopping <= '0';
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terminated <= '0';
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end if;
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elsif dmi_addr = DBG_CORE_GSPR_INDEX then
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gspr_index <= dmi_din(7 downto 0);
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elsif dmi_addr = DBG_CORE_LOG_ADDR then
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log_dmi_addr <= dmi_din(31 downto 0);
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do_dmi_log_rd <= '1';
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elsif dmi_addr = DBG_CORE_LOG_TRIGGER then
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log_dmi_trigger <= dmi_din;
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elsif dmi_addr = DBG_CORE_LOG_MTRIGGER then
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log_mem_trigger <= dmi_din;
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end if;
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else
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report("DMI read from " & to_string(dmi_addr));
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end if;
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elsif dmi_read_log_data = '0' and dmi_read_log_data_1 = '1' then
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-- Increment log_dmi_addr after the end of a read from DBG_CORE_LOG_DATA
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log_dmi_addr(LOG_INDEX_BITS + 1 downto 0) <=
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std_ulogic_vector(unsigned(log_dmi_addr(LOG_INDEX_BITS+1 downto 0)) + 1);
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do_dmi_log_rd <= '1';
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end if;
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dmi_read_log_data_1 <= dmi_read_log_data;
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if dmi_req = '1' and dmi_addr = DBG_CORE_LOG_DATA then
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dmi_read_log_data <= '1';
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else
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dmi_read_log_data <= '0';
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end if;
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-- Set core stop on terminate. We'll be stopping some time *after*
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-- the offending instruction, at least until we can do back flushes
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-- that preserve NIA which we can't just yet.
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if terminate = '1' then
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stopping <= '1';
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terminated <= '1';
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end if;
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end if;
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end if;
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end process;
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gspr_access: process(clk)
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variable valid : std_ulogic;
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variable sel : spr_selector;
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variable isram : std_ulogic;
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variable raddr : ramspr_index;
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variable odd : std_ulogic;
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begin
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if rising_edge(clk) then
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dbg_gpr_req <= '0';
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dbg_spr_req <= '0';
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dbg_ls_spr_req <= '0';
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if rst = '0' and dmi_req = '1' and dmi_addr = DBG_CORE_GSPR_DATA then
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if gspr_index(5) = '0' then
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dbg_gpr_req <= '1';
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elsif gspr_index(4 downto 2) = "111" then
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dbg_ls_spr_req <= '1';
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else
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dbg_spr_req <= '1';
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end if;
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end if;
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-- Map 0 - 0x1f to GPRs, 0x20 - 0x3f to SPRs, and 0x40 - 0x5f to FPRs
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dbg_gpr_addr <= gspr_index(6) & gspr_index(4 downto 0);
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dbg_ls_spr_addr <= gspr_index(1 downto 0);
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-- For SPRs, use the same mapping as when the fast SPRs were in the GPR file
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valid := '1';
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sel := "000";
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isram := '1';
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raddr := (others => '0');
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odd := '0';
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case gspr_index(4 downto 0) is
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when 5x"00" =>
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raddr := RAMSPR_LR;
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when 5x"01" =>
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odd := '1';
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raddr := RAMSPR_CTR;
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when 5x"02" | 5x"03" =>
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odd := gspr_index(0);
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raddr := RAMSPR_SRR0;
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when 5x"04" | 5x"05" =>
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odd := gspr_index(0);
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raddr := RAMSPR_HSRR0;
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when 5x"06" | 5x"07" =>
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odd := gspr_index(0);
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raddr := RAMSPR_SPRG0;
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when 5x"08" | 5x"09" =>
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odd := gspr_index(0);
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raddr := RAMSPR_SPRG2;
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when 5x"0a" | 5x"0b" =>
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odd := gspr_index(0);
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raddr := RAMSPR_HSPRG0;
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when 5x"0c" =>
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isram := '0';
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sel := SPRSEL_XER;
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when 5x"0d" =>
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raddr := RAMSPR_TAR;
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when others =>
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valid := '0';
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end case;
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dbg_spr_addr <= isram & sel & std_ulogic_vector(raddr) & odd;
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spr_index_valid <= valid;
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end if;
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end process;
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-- Core control signals generated by the debug module
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core_stop <= stopping and not do_step;
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core_rst <= do_reset;
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icache_rst <= do_icreset;
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terminated_out <= terminated;
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-- Logging RAM
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maybe_log: if LOG_LENGTH > 0 generate
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subtype log_ptr_t is unsigned(LOG_INDEX_BITS - 1 downto 0);
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type log_array_t is array(0 to LOG_LENGTH - 1) of std_ulogic_vector(255 downto 0);
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signal log_array : log_array_t;
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signal log_rd_ptr : log_ptr_t;
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signal log_wr_ptr : log_ptr_t;
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signal log_toggle : std_ulogic;
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signal log_wr_enable : std_ulogic;
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signal log_rd_ptr_latched : log_ptr_t;
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signal log_rd : std_ulogic_vector(255 downto 0);
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signal log_dmi_reading : std_ulogic;
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signal log_dmi_read_done : std_ulogic;
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function select_dword(data : std_ulogic_vector(255 downto 0);
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addr : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
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variable firstbit : integer;
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begin
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assert not is_X(addr);
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firstbit := to_integer(unsigned(addr(1 downto 0))) * 64;
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return data(firstbit + 63 downto firstbit);
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end;
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attribute ram_style : string;
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attribute ram_style of log_array : signal is "block";
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attribute ram_decomp : string;
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attribute ram_decomp of log_array : signal is "power";
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begin
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-- Use MSB of read addresses to stop the logging
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log_wr_enable <= not (log_read_addr(31) or log_dmi_addr(31) or log_dmi_trigger(1) or log_mem_trigger(1));
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log_ram: process(clk)
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begin
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if rising_edge(clk) then
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if log_wr_enable = '1' then
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assert not is_X(log_wr_ptr);
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log_array(to_integer(log_wr_ptr)) <= log_data;
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end if;
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if is_X(log_rd_ptr_latched) then
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log_rd <= (others => 'X');
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else
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log_rd <= log_array(to_integer(log_rd_ptr_latched));
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end if;
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end if;
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end process;
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log_buffer: process(clk)
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variable b : integer;
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variable data : std_ulogic_vector(255 downto 0);
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begin
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if rising_edge(clk) then
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if rst = '1' then
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log_wr_ptr <= (others => '0');
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log_toggle <= '0';
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log_rd_ptr_latched <= (others => '0');
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elsif log_wr_enable = '1' then
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if log_wr_ptr = to_unsigned(LOG_LENGTH - 1, LOG_INDEX_BITS) then
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log_toggle <= not log_toggle;
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end if;
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log_wr_ptr <= log_wr_ptr + 1;
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end if;
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if do_dmi_log_rd = '1' then
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log_rd_ptr_latched <= unsigned(log_dmi_addr(LOG_INDEX_BITS + 1 downto 2));
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else
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log_rd_ptr_latched <= unsigned(log_read_addr(LOG_INDEX_BITS + 1 downto 2));
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end if;
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if log_dmi_read_done = '1' then
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log_dmi_data <= select_dword(log_rd, log_dmi_addr);
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else
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log_read_data <= select_dword(log_rd, log_read_addr);
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end if;
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log_dmi_read_done <= log_dmi_reading;
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log_dmi_reading <= do_dmi_log_rd;
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do_log_trigger <= '0';
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if log_data(42) = log_dmi_trigger(63) and
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log_data(41 downto 0) = log_dmi_trigger(43 downto 2) and
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log_dmi_trigger(0) = '1' then
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do_log_trigger <= '1';
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end if;
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do_log_mtrigger <= '0';
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if (wb_snoop_in.cyc and wb_snoop_in.stb and wb_snoop_in.we) = '1' and
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wb_snoop_in.adr = log_mem_trigger(wishbone_addr_bits + wishbone_log2_width - 1
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downto wishbone_log2_width) and
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log_mem_trigger(0) = '1' then
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do_log_mtrigger <= '1';
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end if;
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end if;
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end process;
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log_write_addr(LOG_INDEX_BITS - 1 downto 0) <= std_ulogic_vector(log_wr_ptr);
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log_write_addr(LOG_INDEX_BITS) <= '1';
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log_write_addr(31 downto LOG_INDEX_BITS + 1) <= (others => '0');
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end generate;
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no_log: if LOG_LENGTH = 0 generate
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begin
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log_read_data <= (others => '0');
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log_write_addr <= x"00000001";
|
|
end generate;
|
|
|
|
end behave;
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|