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microwatt/litedram/gen-src
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Michael Neuling 57604c1a6e
Merge pull request from ozbenh/uart16550 
Add support for standard 16550 style UART
..
sdram_init Merge pull request from ozbenh/uart16550
arty.yml litedram: Remove old "VexRiscV" based initializations
dram-init-mem.vhdl litedram: Fix DRAM init mem using too many address bits
generate.py litedram: Remove old "VexRiscV" based initializations
nexys-video.yml litedram: Remove old "VexRiscV" based initializations
no-init-mem.vhdl litedram: Split the init memory from the main wrapper
sim.yml litedram: Remove old "VexRiscV" based initializations