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Benjamin Herrenschmidt a3857aac94 litedram: Add an L2 cache with store queue ... This adds a cache between the wishbone and litedram with the following features (at this point, it's still evolving) - 128 bytes line width in order to have a reasonable amount of litedram pipelining on the 128-bit wide data port. - Configurable geometry otherwise - Stores are acked immediately on wishbone whether hit or miss (minus a 2 cycles delay if there's a previous load response in the way) and sent to LiteDRAM via 8 entries (configurable) store queue Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		4 years ago
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sdram_init	litedram: Add an L2 cache with store queue	4 years ago
arty.yml	litedram: Update to new LiteX/LiteDRAM version	4 years ago
dram-init-mem.vhdl	litedram: Add support for booting without BRAM	4 years ago
generate.py	litedram: Add simulation support	4 years ago
nexys-video.yml	litedram: Update to new LiteX/LiteDRAM version	4 years ago
no-init-mem.vhdl	litedram: Split the init memory from the main wrapper	4 years ago
sim.yml	litedram: Add simulation support	4 years ago