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35 lines
1.3 KiB
YAML
35 lines
1.3 KiB
YAML
# Based on orangecrab-85-0.2.yml and arty.yml
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{
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"cpu": "None", # CPU type (ex vexriscv, serv, None)
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"device": "LFE5UM5G-85F-8BG554I",
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"memtype": "DDR3", # DRAM type
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"cmd_latency": 0,
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"sdram_module": "MT41K256M16", # SDRAM modules of the board or SO-DIMM
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"sdram_module_nb": 2, # Number of byte groups
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"sdram_rank_nb": 1, # Number of ranks
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"sdram_phy": "ECP5DDRPHY", # Type of FPGA PHY
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# Electrical ---------------------------------------------------------------
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"rtt_nom": "60ohm", # Nominal termination. (Default)
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"rtt_wr": "60ohm", # Write termination. (Default)
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"ron": "34ohm", # Output driver impedance. (Default)
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# Frequency ----------------------------------------------------------------
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"input_clk_freq": 100e6, # Input clock frequency
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"sys_clk_freq": 50e6, # System clock frequency (DDR_clk = 4 x sys_clk)
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"init_clk_freq": 50e6, # ?
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# Core ---------------------------------------------------------------------
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"cmd_buffer_depth": 16, # Depth of the command buffer
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# User Ports ---------------------------------------------------------------
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"user_ports": {
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"native_0": {
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"type": "native",
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"block_until_ready": False,
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},
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},
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}
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