A tiny Open POWER ISA softcore written in VHDL 2008

openpower ppc64le processor vhdl

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Anton Blanchard a5d31bb554 Merge pull request #24 from antonblanchard/cr_file_cleanup Rework CR file and add forwarding		5 years ago
fpga	Cmod A7-35 support	5 years ago
hello_world	Rebuild hello world assuming a 50MHz clock	5 years ago
scripts	Fix verific script with new VHDL files	5 years ago
tests	Initial import of microwatt	5 years ago
.gitignore	Initial import of microwatt	5 years ago
.travis.yml	A few Travis CI fixes	5 years ago
LICENSE	Initial import of microwatt	5 years ago
Makefile	Rework SOC reset	5 years ago
README.md	Add pretty gif demo of MicroPython on Microwatt to README.md	5 years ago
common.vhdl	Rework CR file and add forwarding	5 years ago
core.vhdl	Use a better input signal in writeback	5 years ago
core_tb.vhdl	micropython only requires 512kB of BRAM	5 years ago
cr_file.vhdl	Rework CR file and add forwarding	5 years ago
crhelpers.vhdl	Initial import of microwatt	5 years ago
decode1.vhdl	Rework CR file and add forwarding	5 years ago
decode2.vhdl	Rework CR file and add forwarding	5 years ago
decode_types.vhdl	Initial import of microwatt	5 years ago
execute1.vhdl	Remove dynamic ranges from code	5 years ago
execute2.vhdl	Initial import of microwatt	5 years ago
fetch1.vhdl	Initial import of microwatt	5 years ago
fetch2.vhdl	Initial import of microwatt	5 years ago
glibc_random.vhdl	Initial import of microwatt	5 years ago
glibc_random_helpers.vhdl	Initial import of microwatt	5 years ago
helpers.vhdl	Remove dynamic ranges from code	5 years ago
insn_helpers.vhdl	Rework decode2	5 years ago
loadstore1.vhdl	Initial import of microwatt	5 years ago
loadstore2.vhdl	Stores need to wait for wishbone write ack	5 years ago
microwatt.core	Cmod A7-35 support	5 years ago
multiply.vhdl	Initial import of microwatt	5 years ago
multiply_tb.vhdl	Initial import of microwatt	5 years ago
ppc_fx_insns.vhdl	Remove dynamic ranges from code	5 years ago
register_file.vhdl	Initial import of microwatt	5 years ago
sim_console.vhdl	Initial import of microwatt	5 years ago
sim_console_c.c	Initial import of microwatt	5 years ago
simple_ram_behavioural.vhdl	Initial import of microwatt	5 years ago
simple_ram_behavioural_helpers.vhdl	Initial import of microwatt	5 years ago
simple_ram_behavioural_helpers_c.c	Add missing argument to fprintf warning	5 years ago
simple_ram_behavioural_tb.bin	Initial import of microwatt	5 years ago
simple_ram_behavioural_tb.vhdl	Initial import of microwatt	5 years ago
wishbone_arbiter.vhdl	Initial import of microwatt	5 years ago
wishbone_types.vhdl	Initial import of microwatt	5 years ago
writeback.vhdl	Rework CR file and add forwarding	5 years ago

README.md

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com

git clone https://github.com/mikey/micropython
cd micropython
git checkout powerpc
cd ports/powerpc
make -j$(nproc)
cd ../../../

Microwatt uses ghdl for simulation. Either install this from your distro or build it. Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

Link in the micropython image:

ln -s ../micropython/ports/powerpc/build/firmware.bin simple_ram_behavioural.bin

Now run microwatt, sending debug output to /dev/null:

./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

Install Vivado (I'm using the free 2019.1 webpack edition).
Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh

Install FuseSoC:

pip3 install --user -U fusesoc

Create a working directory and point FuseSoC at microwatt:

mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/

Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board):

fusesoc run --target=nexys_video microwatt --memory_size=8192 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):

fusesoc run --target=nexys_video microwatt

Testing

A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:

make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

Need to implement a simple non pipelined divide
There are a few instructions still to be implemented
Need to add caches and bypassing (in progress)
Need to add supervisor state (in progress)