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Benjamin Herrenschmidt a69a93b466 Split FPGA toplevel from soc ... This will be useful when we start needing different toplevels for different boards. We keep the reset and clock generators in the toplevel as they will eventually be taken over by litedram when we integrate it, and they are more likely to change on different system types. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		5 years ago
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LICENSE	Initial import of microwatt	5 years ago
arty_a7-35.xdc	Merge pull request #20 from antonblanchard/reset-rework2	5 years ago
clk_gen_bypass.vhd	Rework SOC reset	5 years ago
clk_gen_mcmm.vhd	Cmod A7-35 support	5 years ago
clk_gen_plle2.vhd	Rework SOC reset	5 years ago
cmod_a7-35.xdc	Cmod A7-35 support	5 years ago
firmware.hex	Add a few more FPGA related files	5 years ago
hello_world.hex	Rebuild hello world assuming a 50MHz clock	5 years ago
nexys-video.xdc	Rename a few reset signals	5 years ago
nexys_a7.xdc	Merge pull request #20 from antonblanchard/reset-rework2	5 years ago
nodivide.patch	Add a few more FPGA related files	5 years ago
pp_fifo.vhd	Initial import of microwatt	5 years ago
pp_soc_memory.vhd	Fix ghdl build error with pp_soc_memory	5 years ago
pp_soc_uart.vhd	Initial import of microwatt	5 years ago
pp_utilities.vhd	Initial import of microwatt	5 years ago
soc.vhdl	Split FPGA toplevel from soc	5 years ago
soc_reset.vhdl	Rework SOC reset	5 years ago
soc_reset_tb.vhdl	Rework SOC reset	5 years ago
toplevel.vhdl	Split FPGA toplevel from soc	5 years ago