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Paul Mackerras
03f9d7a97e
Currently the test writes to the XICS and then checks that the expected interrupt has happened. This turns into a stbcix instruction followed immediately by a load from the variable that indicates whether an interrupt has happened. It is possible for it to take a few cycles for the store to reach the XICS and the interrupt request signal to come back to the core, particularly with improvements to the load/store unit and dcache. This therefore adds a delay between storing to the XICS and checking for the occurrence of an interrupt, so as to give the signals time to propagate. The delay loop does an arbitrary 10 iterations, and each iteration does two loads and one store to (cacheable) memory. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> |
4 years ago | |
|---|---|---|
| .. | ||
| Makefile | 4 years ago | |
| head.S | 4 years ago | |
| powerpc.lds | 4 years ago | |
| xics.c | 4 years ago | |
| xics.h | 4 years ago | |