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175 lines
5.0 KiB
VHDL
175 lines
5.0 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.wishbone_types.all;
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entity wishbone_bram_tb is
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end wishbone_bram_tb;
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architecture behave of wishbone_bram_tb is
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signal clk : std_ulogic;
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signal rst : std_ulogic := '1';
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constant clk_period : time := 10 ns;
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signal w_in : wishbone_slave_out;
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signal w_out : wishbone_master_out;
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impure function to_adr(a: integer) return std_ulogic_vector is
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begin
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return std_ulogic_vector(to_unsigned(a, w_out.adr'length));
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end;
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begin
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simple_ram_0: entity work.wishbone_bram_wrapper
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generic map (
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RAM_INIT_FILE => "wishbone_bram_tb.bin",
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MEMORY_SIZE => 16
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)
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port map (
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clk => clk,
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rst => rst,
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wishbone_out => w_in,
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wishbone_in => w_out
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);
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clock: process
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begin
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clk <= '1';
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wait for clk_period / 2;
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clk <= '0';
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wait for clk_period / 2;
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end process clock;
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stim: process
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begin
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w_out.adr <= (others => '0');
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w_out.dat <= (others => '0');
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w_out.cyc <= '0';
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w_out.stb <= '0';
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w_out.sel <= (others => '0');
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w_out.we <= '0';
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wait until rising_edge(clk);
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rst <= '0';
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wait until rising_edge(clk);
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w_out.cyc <= '1';
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-- Test read 0
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w_out.stb <= '1';
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w_out.sel <= "11111111";
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w_out.adr <= to_adr(0);
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assert w_in.ack = '0';
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wait until rising_edge(clk);
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w_out.stb <= '0';
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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assert w_in.ack = '1';
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assert w_in.dat(63 downto 0) = x"0706050403020100" report to_hstring(w_in.dat);
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wait until rising_edge(clk);
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assert w_in.ack = '0';
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-- Test read 8
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w_out.stb <= '1';
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w_out.sel <= "11111111";
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w_out.adr <= to_adr(8);
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assert w_in.ack = '0';
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wait until rising_edge(clk);
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w_out.stb <= '0';
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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assert w_in.ack = '1';
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assert w_in.dat(63 downto 0) = x"0F0E0D0C0B0A0908" report to_hstring(w_in.dat);
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wait until rising_edge(clk);
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assert w_in.ack = '0';
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-- Test write byte at 0
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w_out.stb <= '1';
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w_out.sel <= "00000001";
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w_out.adr <= to_adr(0);
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w_out.we <= '1';
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w_out.dat(7 downto 0) <= x"0F";
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assert w_in.ack = '0';
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wait until rising_edge(clk);
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w_out.stb <= '0';
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wait until rising_edge(clk) and w_in.ack = '1';
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wait until rising_edge(clk);
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assert w_in.ack = '0';
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-- Test read back
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w_out.stb <= '1';
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w_out.sel <= "11111111";
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w_out.adr <= to_adr(0);
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w_out.we <= '0';
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assert w_in.ack = '0';
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wait until rising_edge(clk);
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w_out.stb <= '0';
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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assert w_in.ack = '1';
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assert w_in.dat(63 downto 0) = x"070605040302010F" report to_hstring(w_in.dat);
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wait until rising_edge(clk);
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assert w_in.ack = '0';
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-- Test write dword at 4
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w_out.stb <= '1';
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w_out.sel <= "11110000";
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w_out.adr <= to_adr(0);
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w_out.we <= '1';
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w_out.dat(63 downto 32) <= x"BAADFEED";
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assert w_in.ack = '0';
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wait until rising_edge(clk);
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w_out.stb <= '0';
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wait until rising_edge(clk) and w_in.ack = '1';
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wait until rising_edge(clk);
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assert w_in.ack = '0';
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-- Test read back
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w_out.stb <= '1';
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w_out.sel <= "11111111";
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w_out.adr <= to_adr(0);
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w_out.we <= '0';
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assert w_in.ack = '0';
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wait until rising_edge(clk);
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w_out.stb <= '0';
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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assert w_in.ack = '1';
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assert w_in.dat(63 downto 0) = x"BAADFEED0302010F" report to_hstring(w_in.dat);
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wait until rising_edge(clk);
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assert w_in.ack = '0';
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-- Test write qword at 8
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w_out.stb <= '1';
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w_out.sel <= "11111111";
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w_out.adr <= to_adr(8);
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w_out.we <= '1';
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w_out.dat(63 downto 0) <= x"0001020304050607";
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assert w_in.ack = '0';
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wait until rising_edge(clk);
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w_out.stb <= '0';
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wait until rising_edge(clk) and w_in.ack = '1';
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wait until rising_edge(clk);
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assert w_in.ack = '0';
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-- Test read back
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w_out.stb <= '1';
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w_out.sel <= "11111111";
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w_out.adr <= to_adr(8);
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w_out.we <= '0';
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assert w_in.ack = '0';
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wait until rising_edge(clk);
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w_out.stb <= '0';
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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assert w_in.ack = '1';
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assert w_in.dat(63 downto 0) = x"0001020304050607" report to_hstring(w_in.dat);
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wait until rising_edge(clk);
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assert w_in.ack = '0';
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std.env.finish;
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end process;
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end behave;
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