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482 lines
12 KiB
VHDL
482 lines
12 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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package decode_types is
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type insn_type_t is (OP_ILLEGAL, OP_NOP, OP_ADD,
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OP_ATTN, OP_B, OP_BC, OP_BCREG,
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OP_BCD, OP_BPERM, OP_BREV,
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OP_CMP, OP_CMPB, OP_CMPEQB, OP_CMPRB,
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OP_CNTZ, OP_CROP,
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OP_DARN, OP_DCBF, OP_DCBST, OP_DCBT, OP_DCBTST,
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OP_DCBZ, OP_ICBI, OP_ICBT,
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OP_FP_CMP, OP_FP_ARITH, OP_FP_MOVE, OP_FP_MISC,
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OP_DIV, OP_DIVE, OP_MOD,
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OP_EXTS, OP_EXTSWSLI,
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OP_ISEL, OP_ISYNC,
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OP_LOGIC,
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OP_LOAD, OP_STORE,
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OP_MCRXRX, OP_MFCR, OP_MFMSR, OP_MFSPR,
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OP_MTCRF, OP_MTMSRD, OP_MTSPR, OP_MUL_L64,
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OP_MUL_H64, OP_MUL_H32,
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OP_POPCNT, OP_PRTY, OP_RFID,
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OP_RLC, OP_RLCL, OP_RLCR, OP_SC, OP_SETB,
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OP_SHL, OP_SHR,
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OP_SYNC, OP_TLBIE, OP_TRAP,
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OP_XOR,
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OP_ADDG6S,
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OP_FETCH_FAILED
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);
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-- The following list is ordered in such a way that we can know some
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-- things about which registers are accessed by an instruction by its place
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-- in the list. In other words we can decide whether an instruction
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-- accesses FPRs and whether it has an RB operand by doing simple
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-- comparisons of the insn_code for the instruction with a few constants.
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type insn_code is (
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-- The following instructions don't have an RB operand or access FPRs
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INSN_illegal, -- 0
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INSN_fetch_fail,
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INSN_prefix,
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INSN_pnop,
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INSN_addic,
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INSN_addic_dot,
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INSN_addis,
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INSN_addme,
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INSN_addpcis,
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INSN_addze,
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INSN_andi_dot, -- 10
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INSN_andis_dot,
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INSN_attn,
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INSN_b,
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INSN_bc,
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INSN_bcctr,
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INSN_bclr,
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INSN_bctar,
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INSN_brh,
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INSN_brw,
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INSN_brd, -- 20
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INSN_cbcdtd,
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INSN_cdtbcd,
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INSN_cmpi,
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INSN_cmpli,
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INSN_cntlzw,
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INSN_cntlzd,
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INSN_cnttzw,
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INSN_cnttzd,
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INSN_crand,
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INSN_crandc, -- 30
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INSN_creqv,
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INSN_crnand,
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INSN_crnor,
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INSN_cror,
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INSN_crorc,
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INSN_crxor,
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INSN_darn,
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INSN_eieio,
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INSN_extsb,
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INSN_extsh, -- 40
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INSN_extsw,
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INSN_extswsli,
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INSN_isync,
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INSN_lbzu,
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INSN_ld,
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INSN_ldu,
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INSN_lhau,
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INSN_lwa,
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INSN_lwzu,
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INSN_mcrf, -- 50
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INSN_mcrxrx,
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INSN_mfcr,
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INSN_mfmsr,
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INSN_mfspr,
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INSN_mtcrf,
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INSN_mtmsr,
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INSN_mtmsrd,
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INSN_mtspr,
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INSN_mulli,
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INSN_neg, -- 60
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INSN_nop,
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INSN_ori,
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INSN_oris,
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INSN_popcntb,
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INSN_popcntw,
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INSN_popcntd,
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INSN_prtyw,
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INSN_prtyd,
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INSN_rfid,
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INSN_rldic, -- 70
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INSN_rldicl,
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INSN_rldicr,
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INSN_rldimi,
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INSN_rlwimi,
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INSN_rlwinm,
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INSN_sc,
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INSN_setb,
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INSN_slbia,
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INSN_sradi,
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INSN_srawi, -- 80
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INSN_stbu,
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INSN_std,
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INSN_stdu,
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INSN_sthu,
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INSN_stwu,
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INSN_subfic,
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INSN_subfme,
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INSN_subfze,
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INSN_sync,
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INSN_tdi, -- 90
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INSN_tlbsync,
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INSN_twi,
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INSN_wait,
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INSN_xori,
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INSN_xoris,
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-- Non-prefixed instructions that have a MLS:D prefixed form and
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-- their corresponding prefixed instructions.
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-- The non-prefixed versions have even indexes so that we can
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-- convert them to the prefixed version by setting bit 0
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INSN_addi, -- 96
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INSN_paddi,
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INSN_lbz,
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INSN_plbz,
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INSN_lha, -- 100
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INSN_plha,
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INSN_lhz,
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INSN_plhz,
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INSN_lwz,
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INSN_plwz,
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INSN_stb,
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INSN_pstb,
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INSN_sth,
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INSN_psth,
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INSN_stw, -- 110
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INSN_pstw,
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-- Slots for non-prefixed opcodes that are 8LS:D when prefixed
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INSN_lhzu, -- 112
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INSN_plwa,
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INSN_op57,
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INSN_pld,
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INSN_op61,
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INSN_pstd,
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-- pad to 128 to simplify comparison logic
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INSN_076, INSN_077,
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INSN_078, INSN_079, INSN_07a, INSN_07b, INSN_07c, INSN_07d, INSN_07e, INSN_07f,
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-- The following instructions have an RB operand but don't access FPRs
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INSN_add,
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INSN_addc,
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INSN_adde, -- 130
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INSN_addex,
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INSN_addg6s,
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INSN_and,
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INSN_andc,
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INSN_bperm,
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INSN_cmp,
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INSN_cmpb,
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INSN_cmpeqb,
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INSN_cmpl,
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INSN_cmprb, -- 140
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INSN_dcbf,
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INSN_dcbst,
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INSN_dcbt,
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INSN_dcbtst,
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INSN_dcbz,
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INSN_divd,
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INSN_divdu,
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INSN_divde,
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INSN_divdeu,
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INSN_divw, -- 150
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INSN_divwu,
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INSN_divwe,
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INSN_divweu,
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INSN_eqv,
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INSN_icbi,
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INSN_icbt,
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INSN_isel,
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INSN_lbarx,
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INSN_lbzcix,
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INSN_lbzux, -- 160
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INSN_lbzx,
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INSN_ldarx,
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INSN_ldbrx,
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INSN_ldcix,
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INSN_ldx,
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INSN_ldux,
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INSN_lharx,
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INSN_lhax,
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INSN_lhaux,
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INSN_lhbrx, -- 170
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INSN_lhzcix,
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INSN_lhzx,
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INSN_lhzux,
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INSN_lwarx,
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INSN_lwax,
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INSN_lwaux,
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INSN_lwbrx,
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INSN_lwzcix,
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INSN_lwzx,
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INSN_lwzux, -- 180
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INSN_modsd,
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INSN_modsw,
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INSN_moduw,
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INSN_modud,
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INSN_mulhw,
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INSN_mulhwu,
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INSN_mulhd,
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INSN_mulhdu,
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INSN_mullw,
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INSN_mulld, -- 190
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INSN_nand,
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INSN_nor,
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INSN_or,
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INSN_orc,
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INSN_rldcl,
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INSN_rldcr,
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INSN_rlwnm,
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INSN_slw,
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INSN_sld,
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INSN_sraw, -- 200
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INSN_srad,
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INSN_srw,
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INSN_srd,
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INSN_stbcix,
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INSN_stbcx,
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INSN_stbx,
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INSN_stbux,
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INSN_stdbrx,
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INSN_stdcix,
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INSN_stdcx, -- 210
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INSN_stdx,
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INSN_stdux,
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INSN_sthbrx,
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INSN_sthcix,
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INSN_sthcx,
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INSN_sthx,
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INSN_sthux,
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INSN_stwbrx,
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INSN_stwcix,
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INSN_stwcx, -- 220
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INSN_stwx,
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INSN_stwux,
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INSN_subf,
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INSN_subfc,
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INSN_subfe,
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INSN_td,
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INSN_tlbie,
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INSN_tlbiel,
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INSN_tw,
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INSN_xor, -- 230
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-- pad to 232 to simplify comparison logic
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INSN_231,
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-- The following instructions have a third input addressed by RC
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INSN_maddld,
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INSN_maddhd,
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INSN_maddhdu,
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-- pad to 256 to simplify comparison logic
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INSN_235,
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INSN_236, INSN_237, INSN_238, INSN_239,
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INSN_240, INSN_241, INSN_242, INSN_243,
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INSN_244, INSN_245, INSN_246, INSN_247,
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INSN_248, INSN_249, INSN_250, INSN_251,
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INSN_252, INSN_253, INSN_254, INSN_255,
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-- The following instructions access floating-point registers
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-- They have an FRS operand, but RA/RB are GPRs
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-- Non-prefixed floating-point loads and stores that have a MLS:D
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-- prefixed form, and their corresponding prefixed instructions.
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INSN_stfd, -- 256
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INSN_pstfd,
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INSN_stfs,
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INSN_pstfs,
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INSN_lfd, -- 260
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INSN_plfd,
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INSN_lfs,
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INSN_plfs,
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-- opcodes that can't have a prefix
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INSN_stfdu, -- 264
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INSN_stfsu,
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INSN_stfdux,
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INSN_stfdx,
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INSN_stfiwx,
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INSN_stfsux,
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INSN_stfsx, -- 270
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-- These ones don't actually have an FRS operand (rather an FRT destination)
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-- but are here so that all FP instructions are >= INST_first_frs.
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INSN_lfdu,
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INSN_lfsu,
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INSN_lfdx,
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INSN_lfdux,
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INSN_lfiwax,
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INSN_lfiwzx,
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INSN_lfsx,
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INSN_lfsux,
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-- These are here in order to keep the FP instructions together
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INSN_mcrfs,
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INSN_mtfsb, -- 280
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INSN_mtfsfi,
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INSN_282, -- padding
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INSN_283,
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INSN_284,
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INSN_285,
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INSN_286,
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INSN_287,
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-- The following instructions access FRA and/or FRB operands
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INSN_fabs, -- 288
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INSN_fadd,
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INSN_fadds, -- 290
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INSN_fcfid,
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INSN_fcfids,
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INSN_fcfidu,
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INSN_fcfidus,
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INSN_fcmpo,
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INSN_fcmpu,
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INSN_fcpsgn,
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INSN_fctid,
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INSN_fctidz,
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INSN_fctidu, -- 300
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INSN_fctiduz,
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INSN_fctiw,
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INSN_fctiwz,
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INSN_fctiwu,
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INSN_fctiwuz,
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INSN_fdiv,
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INSN_fdivs,
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INSN_fmr,
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INSN_fmrgew,
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INSN_fmrgow, -- 310
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INSN_fnabs,
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INSN_fneg,
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INSN_fre,
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INSN_fres,
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INSN_frim,
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INSN_frin,
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INSN_frip,
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INSN_friz,
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INSN_frsp,
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INSN_frsqrte, -- 320
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INSN_frsqrtes,
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INSN_fsqrt,
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INSN_fsqrts,
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INSN_fsub,
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INSN_fsubs,
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INSN_ftdiv,
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INSN_ftsqrt,
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INSN_mffs,
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INSN_mtfsf,
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-- pad to 336
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INSN_330, INSN_331, INSN_332, INSN_333, INSN_334, INSN_335,
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-- The following instructions access FRA, FRB (possibly) and FRC operands
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INSN_fmul, -- 336
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INSN_fmuls,
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INSN_fmadd,
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INSN_fmadds,
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INSN_fmsub, -- 340
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INSN_fmsubs,
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INSN_fnmadd,
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INSN_fnmadds,
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INSN_fnmsub,
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INSN_fnmsubs,
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INSN_fsel
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);
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constant INSN_first_rb : insn_code := INSN_add;
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constant INSN_first_rc : insn_code := INSN_maddld;
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constant INSN_first_frs : insn_code := INSN_stfd;
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constant INSN_first_frab : insn_code := INSN_fabs;
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constant INSN_first_frabc : insn_code := INSN_fmul;
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constant INSN_first_mls : insn_code := INSN_addi;
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constant INSN_first_8ls : insn_code := INSN_lhzu;
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constant INSN_first_fp_mls : insn_code := INSN_stfd;
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constant INSN_first_fp_nonmls : insn_code := INSN_stfdu;
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type input_reg_a_t is (NONE, RA, RA_OR_ZERO, RA0_OR_CIA, CIA, FRA);
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type input_reg_b_t is (NONE, RB, CONST_UI, CONST_SI, CONST_SI_HI, CONST_UI_HI, CONST_LI, CONST_BD,
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CONST_DXHI4, CONST_DS, CONST_DQ, CONST_M1, CONST_SH, CONST_SH32, CONST_PSI, FRB);
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type input_reg_c_t is (NONE, RS, RCR, FRC, FRS);
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type output_reg_a_t is (NONE, RT, RA, FRT);
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type rc_t is (NONE, ONE, RC, RCOE);
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type carry_in_t is (ZERO, CA, OV, ONE);
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constant SH_OFFSET : integer := 0;
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constant MB_OFFSET : integer := 1;
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constant ME_OFFSET : integer := 1;
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constant SH32_OFFSET : integer := 0;
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constant MB32_OFFSET : integer := 1;
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constant ME32_OFFSET : integer := 2;
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constant FXM_OFFSET : integer := 0;
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constant BO_OFFSET : integer := 0;
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constant BI_OFFSET : integer := 1;
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constant BH_OFFSET : integer := 2;
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constant BF_OFFSET : integer := 0;
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constant L_OFFSET : integer := 1;
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constant TOO_OFFSET : integer := 0;
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type unit_t is (ALU, LDST, FPU);
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type facility_t is (NONE, FPU);
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type length_t is (NONE, is1B, is2B, is4B, is8B);
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type repeat_t is (NONE, -- instruction is not repeated
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DUPD); -- update-form load
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type decode_rom_t is record
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unit : unit_t;
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facility : facility_t;
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insn_type : insn_type_t;
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input_reg_a : input_reg_a_t;
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input_reg_b : input_reg_b_t;
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input_reg_c : input_reg_c_t;
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output_reg_a : output_reg_a_t;
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input_cr : std_ulogic;
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output_cr : std_ulogic;
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invert_a : std_ulogic;
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invert_out : std_ulogic;
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input_carry : carry_in_t;
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output_carry : std_ulogic;
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-- load/store signals
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length : length_t;
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byte_reverse : std_ulogic;
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sign_extend : std_ulogic;
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update : std_ulogic;
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reserve : std_ulogic;
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-- multiplier and ALU signals
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is_32bit : std_ulogic;
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is_signed : std_ulogic;
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rc : rc_t;
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lr : std_ulogic;
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sgl_pipe : std_ulogic;
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repeat : repeat_t;
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end record;
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constant decode_rom_init : decode_rom_t := (unit => ALU, facility => NONE,
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insn_type => OP_ILLEGAL, input_reg_a => NONE,
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input_reg_b => NONE, input_reg_c => NONE,
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output_reg_a => NONE, input_cr => '0', output_cr => '0',
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invert_a => '0', invert_out => '0', input_carry => ZERO, output_carry => '0',
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length => NONE, byte_reverse => '0', sign_extend => '0',
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update => '0', reserve => '0', is_32bit => '0',
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is_signed => '0', rc => NONE, lr => '0', sgl_pipe => '0', repeat => NONE);
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end decode_types;
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package body decode_types is
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end decode_types;
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